Porous Interconnect Dielectric Structure for Low Capacitance Adhesion
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Solution Overview
Problem
Challenges arise during the scaling-down process of semiconductor devices, including issues related to improved quality, yield, performance, and reliability, as well as reduced complexity, particularly due to increased parasitic capacitance and outgassing problems.
Innovation Solution
The semiconductor device incorporates a porous top and bottom dielectric layer with a barrier layer to reduce parasitic capacitance and improve adhesion, using a porous structure and a method that includes forming a substrate with a bottom interconnector layer, a bottom dielectric layer, and a top dielectric layer, where the top dielectric layer is porous, and a conductive layer with vertical and horizontal segments connected by liners, enhancing adhesion and reducing capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the dimensions of semiconductor devices are scaled down to improve computing ability, then device density and computing performance are improved, but parasitic capacitance increases and manufacturing complexity increases
Solution Approach 1:
The patent employs porous dielectric layers (low-k materials) with controlled porosity (20-80%) to reduce parasitic capacitance in scaled-down semiconductor devices. The porous structure provides lower dielectric constant while maintaining mechanical integrity, enabling continued device scaling without excessive capacitance buildup that would limit computing performance
Solution Approach 2:
The patent uses composite dielectric structures combining organic and inorganic materials (e.g., siloxane-based materials with metal oxides) to achieve optimal balance between low dielectric constant, mechanical strength, and adhesion properties. This composite approach allows simultaneous improvement of electrical performance and structural reliability in scaled devices
2Reliability
If porous dielectric layers are used to reduce parasitic capacitance, then electrical performance is improved, but outgassing problems occur during fabrication
Solution Approach 1:
The patent performs preliminary outgassing treatments during the fabrication process, including controlled heating and vacuum treatments before final device assembly. This preliminary action removes volatile organic compounds from the porous dielectric layers, preventing outgassing issues during subsequent processing and ensuring long-term device reliability
Solution Approach 2:
The patent controls the porous structure formation process to create a dielectric layer that, while inherently prone to outgassing, actually benefits from the same porosity that reduces capacitance. By carefully controlling pore size distribution and material composition, the outgassing is minimized while maintaining the low-k electrical properties
3Reliability
If porous dielectric layers are used to reduce parasitic capacitance, then device performance is improved, but adhesion between layers deteriorates
Solution Approach 1:
The patent applies different material compositions and porosity levels to different regions of the dielectric structure. The porous low-k material is used in regions where capacitance reduction is critical, while denser materials or adhesion-promoting interfacial layers are applied at interfaces where mechanical bonding is essential. This local differentiation maintains both electrical performance and structural integrity
Solution Approach 2:
The patent introduces interfacial adhesion layers or treatment layers between the porous dielectric and adjacent structures. These intermediary layers provide chemical bonding sites that bridge the porous structure with surrounding materials, preventing delamination while preserving the low-capacitance benefits of the porous dielectric
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design improves semiconductor device performance by reducing parasitic capacitance and preventing outgassing, thereby enhancing reliability and adhesion, while maintaining structural integrity.
Implementation Method 1
The top dielectric layer is porous
Implementation Method 2
reduce parasitic capacitance
Implementation Method 3
the barrier layer may prevent outgassing issues of the porous layers
Implementation Method 4
the bottom glue layer and the top glue layer may also improve the adhesion
Data Source
AI summary
The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a bottom interconnector layer positioned in the substrate; a bottom dielectric layer positioned on the substrate; an interconnector structure positioned along the bottom dielectric layer, positioned on the bottom interconnector layer, and positioned on the bottom dielectric layer; a plurality of liners laterally positioned between the bottom dielectric layer and the interconnector structure and vertically positioned between the interconnector structure and the bottom interconnector layer; a top glue layer conformally positioned on the bottom dielectric layer and the interconnector structure; a top dielectric layer positioned surrounding the top glue layer. A top surface of the top glue layer and a top surface of the top dielectric layer are substantially coplanar. The top dielectric layer is porous.