Porous Mesa Semiconductor Layers for Lattice-Mismatched Epitaxy
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Solution Overview
Problem
The growth of semiconductor devices with high lattice constant mismatch to underlying layers is challenging due to increased defect density and phase separation, particularly in InGaN and InGaAIP materials, which affects crystalline quality and electrical properties.
Innovation Solution
A method involving electrochemical porosification of semiconductor layers to reduce the holding force between sapphire substrates and layers, allowing for epitaxial growth with minimal lattice constant adjustment, using a subcarrier and layer sequences with doped and undoped semiconductor materials, and forming mesa structures to compensate for lattice constant differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If thick buffer layers or gradually matched buffers are used to reduce lattice mismatch, then crystalline quality improves, but manufacturing complexity and electrical properties deteriorate
Solution Approach 1:
The patent applies electrochemical porosification to create a porous first layer with controlled porosity (20-90 volume-%). This porous structure reduces the holding force between the sapphire substrate and the layer sequence, allowing strain compensation without requiring thick buffer layers. The porous structure enables high crystalline quality growth of layers with large lattice constant mismatches while avoiding the manufacturing complexity of thick or gradually matched buffers.
2Manufacturing precision
If electrochemical porosification is applied to reduce holding force and strain, then epitaxial growth quality improves, but manufacturing process complexity increases
Solution Approach 1:
The patent utilizes electrochemical porosification to fundamentally change the physical structure of the first layer by controlling porosity parameters (20-90 volume-%). This parameter change reduces the holding force between layers, enabling high-quality epitaxial growth of materials with large lattice constant mismatches. The process is integrated into the existing manufacturing flow, adding a controllable step that improves growth quality without excessive complexity increase.
3Manufacturing precision
If mesa structures are formed in porosified layers, then lattice constant mismatch compensation improves, but manufacturing steps increase
Solution Approach 1:
The patent forms mesa structures (recesses or trenches) in the porosified first layer to segment the structure and create localized strain compensation zones. These mesa structures, combined with the porous structure, provide enhanced compensation for large lattice constant mismatches. The segmentation approach allows precise control of strain distribution while integrating into the existing porosification process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces strain and defect density, enabling high-quality epitaxial growth and functional semiconductor layer sequences with improved electrical properties by compensating for lattice constant mismatches through porosification and mesa structuring.
Implementation Method 1
The first layer is electrochemically porosified in a following step, wherein a porosity degree is at least 20 volume-%
Implementation Method 2
Through porosification, intermediate or hollow spaces are inserted into the structure of the first layer. These voids allow to compensate for distortions without defects occurring in increased numbers in a layer deposited on this porosified layer
Implementation Method 3
By means of an optional additional mesa structure, this effect is further enhanced. In some material systems, mesa structuring with porosification of the first layer is particularly suitable for compensating even larger differences in the lattice constant
Data Source
AI summary
In an embodiment a method for manufacturing a semiconductor body includes providing an subcarrier, generating a layer sequence with a first layer having a doped semiconductor material and a second layer deposited thereon, the second layer having an undoped semiconductor material, providing an electrochemical porosification of the first layer, wherein a degree of porosity is at least 20% by volume, forming mesa structures in the second layer and at least partially in the porous first layer and epitaxially producing a functional layer sequence having at least one planar third layer which is applied to the second layer comprising the mesa structures, wherein the at least one planar third layer has a specific lattice constant which is different from a lattice constant of the second layer.