3D Semiconductor Device With Porous Silicon Layer Transfer
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Solution Overview
Problem
Current 3D integrated circuit technologies face challenges in heat removal and lattice structure damage during the hydrogen implantation process, leading to high temperature thermal treatments that can damage underlying devices and interconnect layers, and also struggle with throughput and cost in die-to-wafer integration.
Innovation Solution
The development of a 3D semiconductor device fabrication method that includes forming a low porosity layer and a high porosity layer on a wafer, allowing for ultra-thin die construction and precise die alignment with less than 400 nm error, enabling efficient die-to-wafer bonding and heat management through epitaxial layer growth and thermal via structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If hydrogen implantation is used to form detaching layer, then layer transfer is enabled, but lattice structure damage occurs requiring high temperature thermal treatment
Solution Approach 1:
A porous silicon intermediate layer is introduced between the donor wafer and the device layer. This porous layer acts as a mediator that can be selectively removed to enable layer transfer without requiring hydrogen implantation into the device layer, thus avoiding lattice damage while still achieving the detaching function
Solution Approach 2:
Porous silicon is used as the detaching layer material. The porous structure provides high surface area and ease of removal through selective etching, enabling layer transfer without the need for hydrogen implantation and subsequent high temperature annealing that would damage the lattice structure
2Stability of the object's composition
If high temperature thermal treatment is applied to cure lattice damage, then lattice structure is recovered, but underlying devices and interconnect layers are damaged
Solution Approach 1:
The porous silicon layer serves as a sacrificial intermediate that can be removed selectively. This eliminates the need for high temperature thermal treatment to cure lattice damage, thereby protecting underlying devices and interconnect layers from thermal damage while still enabling layer transfer
Solution Approach 2:
The porous silicon detaching layer is formed in advance before device fabrication. This preliminary structure enables subsequent layer transfer and removal operations without requiring high temperature processing, thus preventing thermal damage to devices that would otherwise need to be processed at high temperatures
3Productivity
If conventional die-to-wafer integration is used, then 3D stacking is achieved, but throughput and cost efficiency are reduced
Solution Approach 1:
The invention transitions from conventional 2D die-to-wafer integration to a 3D approach using porous silicon layer transfer technology. This enables stacking of multiple device layers with precise alignment and integration, significantly increasing productivity and throughput while reducing manufacturing costs through wafer-level processing
Solution Approach 2:
Porous silicon is used as a sacrificial layer that enables efficient die-to-wafer integration. The porous structure allows for selective removal and layer transfer, facilitating high-throughput 3D stacking and heterogeneous integration while reducing manufacturing complexity and cost
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances heat removal efficiency, reduces device cost, and increases integration throughput by allowing for the construction of 3D ICs with improved alignment precision and reduced thermal damage, enabling more efficient and cost-effective 3D IC fabrication.
Implementation Method 1
The porous silicon layer is removed, transferring the device layer to the handle wafer
Implementation Method 2
enabling efficient die-to-wafer bonding and heat management through epitaxial layer growth and thermal via structures
Data Source
AI summary
A 3D semiconductor device and structure, the device including: a first die including first transistors and first interconnect, overlaid by a second die including second transistors and second interconnect, where the first die has a first die area and the second die has a second die area, where the first die area is at least 10% larger than the second die area, where the second die is aligned to the first die with less than 400 nm alignment error, where second die includes an array of memory cells, and where the first die includes decoders for the array.