Porous Solid Electrolytic Capacitor for High-Frequency Noise Suppression
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Solution Overview
Problem
Conventional capacitors, especially those with MIM structures, struggle to meet the large capacitance requirements of high-frequency CPU carrier boards due to limited available capacitance per area unit, and the common approach of using SMD capacitors is bottlenecked by restricted space and increasing noise bandwidth.
Innovation Solution
A solid electrolytic capacitor design featuring a substrate with a porous structure of varying depths, an oxide layer, a conductive polymer material layer, and conductive sheets, along with vias for electrical connection, which allows for higher capacitance values and reduced parasitic inductance by alternating capacitance regions and electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If MIM structure capacitors are used, then the device complexity is reduced, but the capacitance per area unit is limited and cannot satisfy large capacitance requirements
Solution Approach 1:
The patent employs a porous substrate structure where the substrate contains numerous pores that increase the effective surface area available for capacitance formation. The porous structure allows the capacitor to achieve higher capacitance per area unit by utilizing the increased surface area provided by the pores, while maintaining the simplicity of the MIM structure.
Solution Approach 2:
The patent introduces vertical dimensionality by creating a porous three-dimensional structure instead of a flat two-dimensional surface. This dimensional transition increases the effective area for capacitance without increasing the planar footprint, thereby achieving higher capacitance per area unit while keeping the device structure relatively simple.
2Object-affected harmful factors
If SMD capacitors are placed near power/ground pins, then power noises are lowered, but the restricted area of the IC carrier board limits the amount of capacitors that can be used
Solution Approach 1:
The patent merges the capacitor function directly into the carrier board structure by embedding the capacitor within the substrate itself. This integration combines the substrate and capacitor into a single component, eliminating the need for separate SMD capacitors and freeing up board area while maintaining the noise suppression function.
Solution Approach 2:
The substrate serves multiple functions: it provides mechanical support for the circuit board and simultaneously functions as the capacitor structure. This multi-functionality allows the same component to fulfill both structural and electrical energy storage/dissipation roles, reducing the need for additional components and board space.
3Adaptability or versatility
If the noise bandwidth becomes broader for multiple functionality systems, then the system functionality is enhanced, but the common approach for lowering power noises becomes insufficient
Solution Approach 1:
The patent applies different pore depths in different regions of the substrate to create localized capacitance characteristics. By varying the pore depth distribution, the capacitor can provide different capacitance values for different frequency ranges, enabling effective noise suppression across a broad bandwidth while supporting multiple system functionalities.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively increases capacitance per area and reduces parasitic inductance, enabling the capacitor to effectively suppress wideband noise and meet the capacitance demands of high-frequency circuit systems.
Implementation Method 1
The substrate has a first electrode and a porous structure, in which the first electrode has a first surface and a second surface opposite to the first surface. The porous structure is disposed on the second surface
Implementation Method 2
The oxide layer, disposed on a surface of the porous structure. The second electrode is disposed on the oxide layer
Implementation Method 3
The second electrode is disposed on the oxide layer and includes a conductive polymer material layer
Data Source
AI summary
A capacitor and a circuit board having the same are provided. The capacitor includes a substrate, an oxide layer, a second electrode, an insulating layer, a plurality of conductive sheets and a plurality of vias. The substrate includes a first electrode and a porous structure. The porous structure in at least of two distribution regions has different depths. An oxide layer is disposed on the surface of the porous structure. The second electrode is disposed on the oxide layer and includes a conductive polymer material. The insulating layer disposed on the second electrode has a third and a fourth surfaces. The fourth surface of the insulating layer is connected with the second electrode. The conductive sheets are disposed on the first surface of the first electrode and the third surface of the insulating layer and electrically connected with the corresponding vias according to different polarities.