Post-Gate Dielectric Processing to Protect High-K Layers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current FinFET devices face gate leakage issues, leading to increased power consumption and reduced reliability, which degrades their performance, and the existing fabrication methods are costly and damage the high-K dielectric layer.
Innovation Solution
A post HK dielectric layer process is introduced, where a capping layer including HK and Si materials is formed and annealed within a single tool, and then removed using a wet etching process, avoiding dry etching to protect the HK dielectric layer, thereby improving effective oxide thickness scaling, reducing fabrication costs, and enhancing device reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If dry etching is used to remove the capping layer, then the capping layer can be removed, but the high-K dielectric layer is damaged
Solution Approach 1:
The patent replaces the mechanical/physical dry etching process with a chemical wet etching process. The wet etching uses chemical solutions to selectively remove the capping layer without the physical bombardment and damage caused by dry etching plasma, thereby protecting the high-K dielectric layer while achieving capping layer removal.
Solution Approach 2:
The patent changes the etching parameters by switching from dry to wet chemistry. This involves using specific wet etchants with controlled concentration, temperature, and exposure time to achieve selective removal of the capping layer while maintaining the integrity of the underlying high-K dielectric layer.
2Productivity
If the high-K dielectric layer is damaged, then fabrication can proceed, but gate leakage increases and reliability decreases
Solution Approach 1:
The patent applies preliminary protective action by using wet etching before any potential damage can occur to the high-K dielectric layer. This preventive approach ensures that the dielectric layer remains intact throughout the capping layer removal process, preventing gate leakage issues before they arise.
Solution Approach 2:
The wet etching process acts as an intermediary method between the capping layer and the high-K dielectric layer. It provides a gentle, selective removal mechanism that intermediates the harsh effects of dry etching, allowing capping layer removal while mediating protection for the sensitive dielectric layer.
3Ease of manufacture
If conventional fabrication methods are used, then processing can be completed, but fabrication costs are high
Solution Approach 1:
The patent employs a disposable wet etching process that is simpler and less expensive than conventional dry etching equipment and processes. The wet etching can be performed with standard equipment and chemical solutions, reducing the need for complex, expensive vacuum chambers and plasma generation systems.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach mitigates gate leakage, improves device reliability, and reduces fabrication costs by protecting the HK dielectric layer and optimizing the capping layer formation and removal process.
Implementation Method 1
performing an annealing process to the capping layer
Data Source
AI summary
Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a first semiconductor stack and a second semiconductor stack over a substrate, wherein each of the first and second semiconductor stacks includes semiconductor layers stacked up and separated from each other; a dummy spacer between the first and second semiconductor stacks, wherein the dummy spacer contacts a first sidewall of each semiconductor layer of the first and second semiconductor stacks; and a gate structure wrapping a second sidewall, a top surface, and a bottom surface of each semiconductor layer of the first and second semiconductor stacks.