Post-Metallization Fin Isolation for Uninterrupted Gate Deposition
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Solution Overview
Problem
The formation of gate structures in integrated circuits is disrupted by the presence of fin cut structures, leading to challenges in forming semiconductor devices in memory or logic cells, particularly due to interference during the deposition of gate materials.
Innovation Solution
Forming fin cut structures after the gate structure has been completed, allowing for the selective removal of gate dielectric and conductive layers, and introducing isolation structures to avoid shorting issues by directly abutting the conductive gate layers with the fin cut structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fin cut structures are formed before gate metallization, then fin isolation can be achieved, but gate structure deposition is disrupted and manufacturing complexity increases
Solution Approach 1:
The gate structure is formed first before the fin cut structure, reversing the conventional sequence. This preliminary formation of the gate structure allows subsequent fin cut formation without disrupting gate deposition processes, as the gate is already in place to define the isolation boundaries.
Solution Approach 2:
The conventional sequence of forming fin cut structures before gate metallization is inverted. By forming the gate structure first and then creating the fin cut isolation structures, the patent eliminates the interference problem where fin cuts would disrupt gate deposition, while still achieving the required electrical isolation.
2Productivity
If cell size is reduced to improve integration density, then more devices fit in limited space, but manufacturing precision requirements increase
Solution Approach 1:
The fin structure is segmented by forming fin cut structures that divide the fin into separate regions. This segmentation allows for precise control over the electrical isolation boundaries while maintaining compact overall device dimensions, enabling higher integration density without compromising manufacturing precision.
Solution Approach 2:
The fin cut structures create localized regions with different electrical properties within the fin. By controlling the position and extent of these cuts, the patent achieves precise local isolation where needed while maintaining the overall compact structure required for high integration density.
3Device complexity
If gate structure and fin cut structure are formed simultaneously, then process steps are reduced, but interference and shorting risks increase
Solution Approach 1:
The gate structure is formed as a preliminary step before creating the fin cut isolation structures. This sequence ensures that the gate structure is already in place to define the boundaries and prevent shorting, while the fin cuts are subsequently formed to complete the isolation without interfering with gate formation.
Data Source
AI summary
Techniques are provided herein to form fin cut structures, or fin isolation structures, after the metal gate has been formed. In an example, a row of semiconductor devices each include a semiconductor region extending in a first direction between a source region and a drain region, and a gate structure extending in a second direction over the semiconductor regions of each neighboring semiconductor device along the row. A fin cut structure that includes a dielectric material interrupts the gate structure and replaces the semiconductor region of one of the semiconductor devices, effectively cutting through the length of the semiconductor device fin (or nanoribbons). The gate structure is formed first followed by removing a portion of the gate structure and removing the semiconductor region of one of the semiconductor devices to form the fin cut structure. In this way, the fin cut structure does not interfere when forming the gate structure.