Post Passivation Interconnects via Laser Ablation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor industry faces challenges in reducing the physical size of semiconductor devices while maintaining integration density, as conventional packaging techniques are costly and inefficient, particularly in forming post-passivation interconnects and under bump metallization structures.
Innovation Solution
The use of laser ablation processes to pattern polymer layers and form seed layers, reducing the need for multiple photo resist layers and associated fabrication steps, thereby simplifying the formation of post-passivation interconnects and under bump metallization structures in wafer-level chip scale packages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional photo resist layer fabrication techniques are used to form post passivation interconnects, then the interconnect structures can be formed with established processes, but the fabrication cost increases and the manufacturing complexity increases due to multiple photo resist layers and associated fabrication steps
Solution Approach 1:
The patent extracts and removes the photo resist layer formation steps from the fabrication process. Instead of using multiple photo resist layers to define patterns, the invention directly forms conductive material layers through deposition and etching processes, eliminating the need for photo resist coating, exposure, and development steps entirely.
Solution Approach 2:
The patent replaces the mechanical/chemical photo resist-based patterning system with a direct physical vapor deposition and etching system. Conductive materials are deposited conformally and then patterned through selective etching, substituting the multi-step photo resist process with a more direct materials deposition and removal approach.
2Productivity
If multiple photo resist layers are used to form post passivation interconnects and under bump metallization, then the patterning can be achieved with conventional techniques, but the manufacturing time increases and productivity decreases
Solution Approach 1:
The patent merges multiple separate patterning operations into a unified process flow. By forming conductive material layers conformally and then performing selective etching in sequence, the invention combines what would otherwise require multiple photo resist layer applications, exposures, and developments into a more integrated deposition-etch-deposition-etch sequence, reducing total process time.
Solution Approach 2:
The patent performs preliminary conformal deposition of conductive material layers before final patterning. This preliminary action of depositing material uniformly across the surface first, then selectively removing portions through etching, allows for more efficient process sequencing compared to forming patterns layer-by-layer with photo resist.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach lowers the fabrication cost of wafer-level chip scale packages by eliminating the need for additional photo resist layers, enhancing the efficiency and cost-effectiveness of the packaging process.
Implementation Method 1
The use of laser ablation processes to pattern polymer layers and form seed layers
Data Source
AI summary
A method of forming post passivation interconnects comprises forming a passivation layer over a substrate, wherein a metal pad is embedded in the passivation layer, depositing a first dielectric layer on the passivation layer, applying a first patterning process to the first dielectric layer to form a first opening, forming a first seed layer over the first opening, filling the first opening with a conductive material, depositing a second dielectric layer on the first dielectric layer, applying a second patterning process to the second dielectric layer to form a second opening, forming an under bump metallization structure over the second opening and mounting an interconnect bump over the under bump metallization structure.