Digital Power Amplifier Cell Timing for Efficient Polar Transmitters
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Solution Overview
Problem
The challenge in wireless communications, particularly for IoT applications, is to minimize power consumption in transceivers while maintaining amplifier linearity, as existing solutions often compromise between power efficiency and linearity, leading to degraded signal quality and increased heat generation.
Innovation Solution
A polar transmission system with a digital power amplifier that uses a bank of amplifier cells and a phase-locked loop with a digitally-controlled oscillator, where the power amplifier's gain is controlled by selectively engaging amplifier cells based on amplitude codewords, and a predistortion circuit to maintain signal quality and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a linear RF power amplifier is used to maintain amplifier linearity, then signal quality is preserved, but power consumption increases and power efficiency decreases
Solution Approach 1:
The power amplifier is divided into multiple parallel amplifier cells (first bank and second bank) that can be independently controlled. By selectively engaging specific cells based on the amplitude of the modulated carrier signal, the system achieves variable gain operation with improved power efficiency while maintaining signal quality through coordinated operation of multiple smaller amplification units.
Solution Approach 2:
The system dynamically adjusts the number of engaged amplifier cells based on the instantaneous amplitude of the modulated carrier signal. This dynamic reconfiguration allows the amplifier to operate at optimal efficiency points across varying signal conditions, resolving the contradiction between maintaining linearity and minimizing power consumption.
2Use of energy by moving object
If power efficiency is maximized by selecting efficient power amplifiers, then power consumption decreases, but amplifier linearity deteriorates
Solution Approach 1:
The amplifier is segmented into multiple cells operating in parallel, where each cell can be independently controlled. This segmentation enables the system to achieve high power efficiency by engaging only the necessary number of cells while maintaining overall linearity through the coordinated operation of multiple efficient units rather than relying on a single inefficient linear amplifier.
Solution Approach 2:
Multiple amplifier cells are merged in parallel configuration to achieve the desired output power and linearity. By combining the outputs of multiple efficient cells rather than using a single cell or traditional linear amplifier, the system achieves both high power efficiency and maintained linearity.
3Power
If available power output is maximized from the power amplifier, then transmission power increases, but power consumption and heat generation increase
Solution Approach 1:
The power amplifier is divided into multiple parallel banks of amplifier cells that can be selectively engaged. This segmentation allows the system to maximize available power output by engaging all necessary cells while maintaining high efficiency and minimizing heat generation through optimized operation of individual cells rather than overloading a single amplifier.
Data Source
AI summary
A polar transmitter including a digital power amplifier cell that includes a first circuit and an amplifier circuit. The first circuit is configured to receive a phase modulated carrier signal and to generate a PMOS control signal and an NMOS control signal such that the PMOS control signal and the NMOS control signal have different duty cycles. The amplifier circuit is configured to receive the PMOS control signal at a PMOS transistor and the NMOS control signal at an NMOS transistor. The first circuit is configured to align the PMOS control signal and the NMOS control signal with respect to one another such that a time that the NMOS transistor and the PMOS transistor of the amplifier circuit are simultaneously conducting is minimized. The amplifier circuit is configured to generate an amplified modulated carrier signal in response to the PMOS and NMOS control signals.