Power-Aware Memory Self-Test Unit for IC Yield
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Solution Overview
Problem
Current built-in self-test (BIST) units for integrated circuits face challenges in efficiently testing memory blocks, particularly in reducing testing time and complexity while accurately identifying defects in memory banks that may be independently powered on or off.
Innovation Solution
A memory self-test unit is configured to determine the power status of each memory block and disregard test results from blocks that are powered off, allowing for independent power control and management of memory banks, thereby focusing on valid test data from operational blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the self-test unit tests all memory blocks regardless of power status, then the testing process is simple and uniform, but the testing time increases and test results become inaccurate for powered-off blocks
Solution Approach 1:
The self-test unit determines the power status of each memory block before conducting the actual memory test. This preliminary check allows the system to skip testing powered-off blocks, thereby reducing testing time while maintaining accurate test results for only those blocks that are currently powered on and operational.
2Measurement precision
If the self-test unit includes power status detection capability, then test result accuracy improves, but the device complexity increases
Solution Approach 1:
The self-test unit utilizes an existing power status indication signal that is already generated within the memory system to determine whether memory blocks are powered on or off. By using this intermediary signal, the self-test unit achieves accurate test result determination without requiring complex additional power detection circuitry, thus minimizing the increase in device complexity.
3Ease of manufacture
If all memory blocks are tested uniformly, then the testing process is easier to implement, but the manufacturing yield decreases due to false failures from powered-off blocks
Solution Approach 1:
The self-test unit performs a preliminary power status check on each memory block before executing the memory test. This preliminary action enables the system to selectively test only powered-on blocks, eliminating false failure indications from powered-off blocks and thereby improving manufacturing yield without significantly complicating the testing process implementation.
Data Source
AI summary
Techniques are disclosed relating to testing logic in integrated circuits based on power being received by the integrated circuit. In one embodiment, an integrated circuit includes a memory and a self-test unit. The self-test unit is configured to receive an indication that identifies a memory block as being in a low-power state and to determine whether to disregard test data read from the one or more memory banks. In some embodiments, the self-test unit may be configured to mask a portion of test result related to the test data that the self-test unit has determined to disregard. The self-test unit may include an error validation logic configured to determine a validity of test data received from a memory based on a power activation status (e.g., whether the memory is powered on or off) associated with the memory.