Power Chip Integration Module with Internal Electrodes
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Solution Overview
Problem
Conventional power module packages face challenges such as high component count and mounting costs, lengthy mounting times, damage during jig separation, increased parasitic inductance, and thermal stress in double-sided cooling types, leading to inefficiencies and reduced durability.
Innovation Solution
A power chip integration module integrates multiple semiconductor chips into a single module with a wiring layer and internal electrodes, surrounded by a molding member, reducing component count and eliminating the need for separate jigs, while using an integral spacer for improved thermal resistance and stress dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple semiconductor chips are mounted separately on a lead frame using conventional methods, then each chip can be individually connected and tested, but the number of components increases, mounting time and cost increase, and the risk of damage during jig separation increases
Solution Approach 1:
The patent merges multiple semiconductor chips into a single integrated module structure where chips are pre-connected and packaged together as one unit. This integration reduces the number of separate mounting operations and components while maintaining individual chip connectivity and functionality, directly resolving the contradiction between reliability and device complexity
Solution Approach 2:
The patent performs preliminary actions by pre-assembling and pre-testing the semiconductor chips within an integrated module before final installation. The chips are connected and verified in advance during module fabrication, eliminating the need for separate mounting and testing steps during final assembly, thus reducing mounting time and complexity while ensuring reliability
2Manufacturing precision
If separate jigs are used for each mounting step to ensure precise positioning, then mounting precision can be maintained, but time and manpower are consumed for installing and stacking jigs
Solution Approach 1:
The patent combines multiple mounting operations into a single integrated module assembly process. Instead of using separate jigs for each chip mounting step, the entire module is fabricated and pre-assembled in one location, then installed as a single unit, eliminating the need for multiple jig installations and stackings while maintaining positioning precision through the integrated fabrication process
Solution Approach 2:
The patent performs preliminary positioning and alignment actions during the module fabrication process rather than during final installation. Chips are precisely positioned and connected in advance within the integrated module structure, so that when the module is installed, no additional positioning jigs are needed, thereby improving productivity without sacrificing precision
3Temperature
If package thickness is reduced to improve thermal resistance characteristics, then heat dissipation is improved, but wire density increases causing short-circuit phenomena and increased parasitic inductance
Solution Approach 1:
The patent transitions from planar wire connections to three-dimensional internal electrode structures within the integrated module. By utilizing vertical and lateral electrode extensions embedded in the module structure, electrical connections are established through multiple dimensions rather than relying solely on dense planar wiring, thereby reducing wire density and parasitic inductance while maintaining thin package thickness for improved thermal resistance
Solution Approach 2:
The patent introduces internal electrodes as intermediary connection elements between the semiconductor chips and external terminals. These internal electrodes serve as mediators that provide low-inductance connection paths through the module structure, eliminating the need for dense external wiring and reducing the risk of short-circuit phenomena while allowing thin package design for better thermal management
4Temperature
If metal layers are formed directly on chips for double-sided cooling, then thermal conduction is improved, but thermal stress concentrates on the chip causing damage
Solution Approach 1:
The patent introduces a buffer layer as an intermediary between the metal cooling layers and the semiconductor chip. This buffer layer acts as a stress-absorbing mediator that reduces thermal stress concentration on the chip during thermal cycling, while still allowing efficient thermal conduction from the chip through the metal layers for double-sided cooling
Solution Approach 2:
The patent employs composite material structures consisting of multiple layers including the semiconductor chip, buffer layer, and metal cooling layers. This composite construction combines materials with different mechanical and thermal properties to achieve both efficient thermal conduction and stress distribution, protecting the chip from thermal damage while maintaining cooling effectiveness
Data Source
AI summary
Provided is a power chip integration module including: a first semiconductor chip; a second semiconductor chip; a wiring layer on an upper surface or a lower surface of the first semiconductor chip and the second semiconductor chip to electrically connect the first semiconductor chip and the second semiconductor chip; an internal electrode extending from an internal electrode pad on an upper surface of at least one of the wiring layer, the first semiconductor chip, the second semiconductor chip, and combinations thereof to an external solder pad formed on an installation surface of the first semiconductor chip and the second semiconductor chip; and a first molding member in a shape to surround at least a portion of the first semiconductor chip, the second semiconductor chip, and the internal electrode.