Power Chip 3D Stacked Metal Layers Reduce Parasitic Inductance
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Solution Overview
Problem
High parasitic inductance in data center power supply systems reduces efficiency and increases power consumption, particularly in high-frequency low-voltage Buck circuits, limiting the ability to enhance power density and reduce energy usage in data centers.
Innovation Solution
A power chip design featuring alternately arranged power switches and a metal region with stacked layers, where strip electrodes with the same voltage potential are electrically coupled, reducing the geometrical center distance between switches and capacitor, thereby minimizing parasitic inductance and improving efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional power supply designs are used, then power delivery is achieved, but parasitic inductance is high causing voltage spikes and switching losses
Solution Approach 1:
The patent transitions from planar 2D layout to 3D stacked architecture by introducing multiple metal layers (first metal layer, second metal layer, third metal layer) with vertical vias. This dimensional change allows current paths to extend in the vertical direction, creating shorter and more direct electrical connections between power switches and capacitor, thereby reducing parasitic inductance and switching losses
Solution Approach 2:
The patent embeds the capacitor structure within the power supply circuit by nesting it among the power switches. The capacitor is positioned in the wafer region with its electrodes connected to the metal layers, creating a compact integrated structure where the capacitor is effectively surrounded by and interconnected with the power switches, reducing the geometrical center distance and parasitic inductance
2Power
If power density is increased, then more processing capacity is achieved, but occupied space and power consumption increase
Solution Approach 1:
The patent utilizes the vertical dimension by stacking multiple metal layers (first, second, and third metal layers) above the wafer region. This 3D configuration allows power and signal routing to occur in the vertical direction, significantly reducing the horizontal footprint required for power delivery circuits. The stacked capacitor structure with electrodes in different metal layers further compresses the horizontal space requirement, enabling higher power density in a compact volume
Solution Approach 2:
The patent merges the power switches and capacitor into a single integrated power supply chip. By combining these previously separate components into one device with shared substrates and interconnected metal layers, the patent eliminates the need for external discrete components and interconnectors, thereby reducing the total occupied space while maintaining or enhancing power delivery capability
3Power
If power switches are arranged in bridge circuit, then power conversion is achieved, but parasitic inductance increases due to larger geometrical center distance
Solution Approach 1:
The patent reduces the geometrical center distance between power switches and capacitor by utilizing vertical connections through multiple metal layers and vias. Instead of requiring long horizontal traces to connect the bridge circuit power switches to the capacitor, the design implements direct vertical pathways through the stacked metal structure, dramatically shortening the current path length and reducing parasitic inductance in the bridge circuit configuration
Solution Approach 2:
The patent applies different metal layer configurations to different regions of the power supply chip. The first metal layer, second metal layer, and third metal layer are selectively positioned and connected in different areas to optimize local current paths. This localized optimization ensures that each region of the bridge circuit has the minimal necessary trace length and parasitic inductance for its specific function
Data Source
AI summary
A power chip includes: a first power switch, formed in a wafer region and having a first and a second metal electrodes; a second power switch, formed in the wafer region and having a third and a fourth metal electrodes, wherein the first and second power switches respectively constitute an upper bridge arm and a lower bridge arm of a bridge circuit, and the first and second power switches are alternately arranged along a first direction; and a metal region, at least including a first metal layer, a second metal layer and a third metal layer that are stacked, each metal layer including a first to a third strip electrodes, and strip electrodes with the same voltage potential in two adjacent metal layers are electrically coupled, wherein a routing direction of the strip electrode in the first metal layer is substantially perpendicular to the first direction.