Power Converter PCB Layout for Inductance Balancing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In power conversion devices for hybrid and electric vehicles, there is a need to suppress current unbalancing of control signals while preventing the substrate from becoming excessively large due to the stacking of control signal lines, which affects the performance of power semiconductors.
Innovation Solution
A power conversion device configuration that includes a circuit board with specific wire and resistor arrangements to reduce inductance differences between control signal wires, featuring a first and second power semiconductor element, a first emitter wire, first and second gate wires, a third gate wire, and gate resistors connecting the gate wires over the emitter wire, which helps in balancing the current and reducing substrate size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If control signal lines are stacked in a multi-layer substrate to suppress current unbalancing, then current unbalancing is suppressed, but the control signal substrate becomes larger
Solution Approach 1:
The patent transitions from a planar single-layer layout to a three-dimensional multi-layer stacked configuration. Control signal lines are arranged on different layers and stacked vertically, allowing current paths to be formed in the vertical dimension rather than requiring extended horizontal paths. This reduces the substrate area while maintaining effective current unbalancing suppression through the stacked geometry.
Solution Approach 2:
The patent embeds multiple control signal lines and their associated current paths within a compact stacked structure where lines on different layers are positioned to form nested current loops. The emitter lines on one layer are positioned to face gate lines on adjacent layers, creating nested electromagnetic structures that suppress current unbalancing while minimizing the overall substrate footprint.
2Power
If power semiconductors are connected in parallel to increase output power, then output power is increased, but inductance difference between control signal wires causes current unbalancing
Solution Approach 1:
The patent employs asymmetric positioning of gate lines and emitter lines on different layers to create balanced current paths for parallel-connected power semiconductors. By carefully designing the relative positions and orientations of lines on adjacent layers, the patent compensates for the inherent asymmetry introduced by parallel connections, ensuring equal inductance values and balanced current distribution among all power semiconductor devices.
Solution Approach 2:
The stacked multi-layer configuration creates symmetric current loops where gate lines and emitter lines on adjacent layers form equipotential structures. This geometric arrangement ensures that all parallel-connected power semiconductors experience identical inductance values, achieving equipotential conditions that prevent current unbalancing and enable reliable high-power operation.
Data Source
AI summary
A power conversion device includes first and second power semiconductor elements, and a circuit for transferring a drive signal of the first and second power semiconductor elements. The circuit board includes a first emitter wire which is formed along an arranging direction of the first power semiconductor element and the second power semiconductor element, a first gate wire which is disposed between the first power semiconductor element and the first emitter wire, a second gate wire which is disposed between the second power semiconductor element and the emitter wire, a third gate wire which is disposed to face the first gate wire and the second gate wire with the emitter wire interposed between the third gate wire and the first gate wire and the second gate wire, and a first gate resistor which connects the first gate wire and the third gate wire over the first emitter wire.