Power Device Integration on Common Substrate
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Solution Overview
Problem
Current power management systems for portable electronic devices face challenges in miniaturization and cost due to the high die area allocation for power switches, which limits the integration of power devices and control circuitry on a single IC chip, especially at higher power ranges above five watts, and struggles with high-frequency applications due to parasitic impedances.
Innovation Solution
The integration of power devices and control circuitry on a common silicon substrate using BiCMOS IC fabrication technology with silicon-on-insulator (SOI) substrates and dielectric lateral isolation, enabling a two-die solution that reduces parasitic impedances and allows for higher operating frequencies by using buried wells and trench structures to clamp breakdown voltages and enhance switching performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If power switches are implemented using MOSFET devices with standard fabrication processes, then the manufacturing process is simple with fewer mask steps, but the die area allocated to power switches becomes large, increasing product cost
Solution Approach 1:
The patent changes the fabrication parameters by introducing additional mask steps (increasing from fewer than ten to about 26-36 mask levels) to enable higher integration density. This allows power switches to be implemented with smaller die area by using more precise patterning and additional processing layers, thereby reducing the overall product cost despite the increased manufacturing complexity
Solution Approach 2:
The patent employs a composite fabrication approach that combines multiple fabrication techniques and materials layers to achieve both high integration density and cost-effectiveness. By using advanced photolithography materials, multiple dielectric layers, and sophisticated interconnect structures, the patent enables compact power switch implementation while maintaining manufacturability
2Volume of moving object
If power devices and control circuitry are integrated on a single IC chip, then device miniaturization is achieved, but parasitic impedances increase, limiting high-frequency performance
Solution Approach 1:
The patent utilizes three-dimensional integration techniques and vertical device structures to reduce parasitic impedances. By stacking functional layers vertically and using through-silicon vias for interconnects, the patent minimizes the length of current paths and reduces parasitic inductance and resistance, enabling high-frequency operation in a compact form factor
Solution Approach 2:
The patent introduces intermediary structures such as shield layers, ground planes, and isolation regions between power devices and control circuitry. These intermediary elements act as mediators to reduce electromagnetic coupling and minimize parasitic effects, allowing close integration of power devices and control circuitry while maintaining high-frequency performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables cost-effective miniaturization, reduces power losses, and increases the operating frequency of power management systems, allowing for efficient power conversion across a wider range of power levels while maintaining high-frequency performance.
Implementation Method 1
The clamping diode is operative to locate a breakdown avalanche region between the buried well and the first terminal in the semiconductor structure
Data Source
AI summary
A semiconductor structure for facilitating an integration of power devices on a common substrate includes a first insulating layer formed on the substrate and an active region having a first conductivity type formed on at least a portion of the first insulating layer. A first terminal is formed on an upper surface of the structure and electrically connects with at least one other region having the first conductivity type formed in the active region. A buried well having a second conductivity type is formed in the active region and is coupled with a second terminal formed on the upper surface of the structure. The buried well and the active region form a clamping diode which positions a breakdown avalanche region between the buried well and the first terminal. A breakdown voltage of at least one of the power devices is a function of characteristics of the buried well.