3D Power Device Packaging Reduces Parasitic Inductance
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Solution Overview
Problem
Traditional power semiconductor module packaging structures face issues such as large parasitic inductance, limited heat dissipation, and asymmetrical current dynamic sharing, which hinder high-frequency applications and affect the efficiency, reliability, and electromagnetic compatibility (EMC) of power electric converters.
Innovation Solution
A three-dimensional packaging structure incorporating a heatsink, multiple heat dissipation substrates, direct bond copper substrates, and flexible print circuit boards, forming a half-bridge circuit with parallel and series connections of MOSFET and SBD chips, and utilizing high-conductivity materials and insulating layers to reduce parasitic inductance and enhance heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional lead wire terminals are used for connecting electrodes, then the packaging structure is simple and easy to manufacture, but parasitic inductance increases significantly
Solution Approach 1:
The patent extracts and eliminates the traditional lead wire terminals from the packaging structure. Instead of using separate lead wires to connect electrodes, the invention integrates the electrical connections directly into the substrate and module structure, removing the source of parasitic inductance while maintaining manufacturing feasibility through standardized substrate fabrication processes
Solution Approach 2:
The patent merges the functions of electrode connection and structural support into integrated substrates. The DC link substrate and module substrate serve both as mechanical support structures and as electrical connection pathways, eliminating the need for separate lead wires and reducing parasitic inductance through direct, low-inductance bonding connections
2Power
If multi-chip parallel configuration is adopted to increase power conversion capability, then power rating is improved, but current dynamic sharing becomes asymmetrical and parasitic parameters increase
Solution Approach 1:
The patent employs asymmetrical layout strategies on the DC link substrate to compensate for inherent asymmetries in the multi-chip configuration. By carefully designing the positions and connection paths of different chips and their bonding wires, the invention balances the current distribution and reduces parasitic parameter differences, achieving symmetrical current dynamic sharing despite the physical asymmetry of multiple chips
Solution Approach 2:
The patent applies local optimization techniques to different regions of the substrate, assigning specific chip positions and connection configurations that minimize parasitic parameters for each individual chip while maintaining overall system balance. Each chip's connection path is locally optimized to achieve uniform current sharing across all parallel devices
3Ease of manufacture
If conventional packaging structure is used, then manufacturing process is straightforward, but heat dissipation capability is insufficient
Solution Approach 1:
The patent transitions from conventional two-dimensional planar packaging to a three-dimensional stacked architecture. Multiple functional layers (DC link substrate, module substrate, heat dissipation substrate) are stacked vertically, allowing heat to be conducted in the thickness direction to dedicated heat dissipation paths and sinks, dramatically improving heat dissipation capability while maintaining a compact footprint and straightforward manufacturing process
4Power
If larger substrate area is used to accommodate more chips, then power rating increases, but space utilization of heatsink decreases
Solution Approach 1:
The patent resolves the space conflict by moving the expansion direction from the horizontal plane to the vertical dimension. Multiple chips are arranged on stacked substrates rather than spreading out on a single large substrate, allowing high current ratings to be achieved through vertical stacking while maintaining compact heatsink footprints and high space utilization
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces parasitic inductance, improves heat dissipation, and enhances reliability and space utilization, allowing for direct connection with external circuits and reducing overvoltage and oscillation during switching processes.
Implementation Method 1
a heatsink for integrating the fan, a first heat dissipation substrate, a second heat dissipation substrate, a third heat dissipation substrate
Implementation Method 2
a heatsink for integrating the fan
Implementation Method 3
a first direct bond copper (DBC) substrate, a second DBC substrate, a third DBC substrate
Data Source
AI summary
A three-dimensional packaging structure and a packaging method of power devices. The packaging structure includes power devices, direct copper bonded substrates (i.e., DBC substrates), flexible printed circuit boards (i.e., FPC boards), bonding wires, heat dissipation substrates, decoupling capacitors, a heatsink with integrating the fan, shells, and forms a half-bridge circuit structure composed by the power devices. The power circuit structure is optimized, parasitic inductance in the commutation loop is reduced by mutual inductance cancellation, thus overvoltage and oscillation during the power device switching process can be reduced. Additionally, by using the flexible characteristic of the flexible PCB, a three-dimensional packaging structure is formed and power density is improved.