Power Device Integration on Common Substrate
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Solution Overview
Problem
Current power management systems for portable electronic devices face challenges in miniaturization and cost due to the high product cost of power switches and parasitic impedances, which limit the integration of power devices on a common substrate, especially for high-frequency applications above 1 MHz and power ranges beyond 5 watts.
Innovation Solution
The integration of power devices, including BJTs and MOSFETs, on a common silicon substrate using BiCMOS IC fabrication technology with dielectric lateral isolation, allowing for a two-die solution that reduces parasitic impedances and increases operating frequency, while leveraging chip-scale assembly to minimize packaging costs and volume.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If power switches are integrated on a common substrate with control circuitry, then device miniaturization is achieved, but product cost increases due to large die area allocation to power switches
Solution Approach 1:
The patent divides the power management system into two separate integrated circuits: a first IC containing control circuitry and a second IC containing power switches. This segmentation allows each IC to be optimized independently, reducing the die area required for power switches while maintaining integration benefits. The separation enables cost-effective manufacturing by allocating power switch area only where needed rather than sharing a large common substrate.
Solution Approach 2:
The patent transitions from planar integration on a single substrate to three-dimensional stacking with multiple IC layers. By placing control circuitry on one IC and power switches on another IC in a vertical arrangement, the solution achieves miniaturization without proportionally increasing die area costs. This dimensional transition allows efficient space utilization while maintaining manufacturability.
2Device complexity
If power devices are integrated on a common substrate, then component count is reduced, but parasitic impedances increase limiting high-frequency performance above 1 MHz
Solution Approach 1:
By segmenting the power management system into separate control and power switch ICs, the patent reduces parasitic impedances between these functional blocks. The physical separation eliminates unwanted parasitic inductance and capacitance that would exist in a monolithic integration, enabling high-frequency operation above 1 MHz while maintaining low component count through systematic integration of the segmented modules.
Solution Approach 2:
The patent introduces a driver stage as an intermediary component between the control circuitry IC and power switches IC. This driver stage acts as a buffer that minimizes parasitic impedance effects during signal transmission, enabling high-frequency switching operation while maintaining the benefits of integrated power management with reduced component count.
3Volume of moving object
If power management components are integrated into a single IC chip, then device miniaturization is achieved, but switching losses increase reducing efficiency
Solution Approach 1:
The patent segments the power management system into separate control and power switch ICs, allowing independent optimization of each module for minimal switching losses. The power switch IC can be designed with optimal device geometry and materials for low switching losses, while the control IC can be optimized for efficiency. This segmentation enables achieving both miniaturization through integration and reduced switching losses through specialized design.
Solution Approach 2:
By separating the power switch functionality into a dedicated IC, the patent enables optimization of critical parameters such as switching frequency, duty cycle, and device geometry independently of the control circuitry. This parameter optimization reduces switching losses while maintaining compact form factor, resolving the contradiction between miniaturization and efficiency.
Data Source
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AI summary
A semiconductor structure for facilitating an integration of power devices on a common substrate includes a first insulating layer formed on the substrate and an active region having a first conductivity type formed on at least a portion of the first insulating layer. A first terminal is formed on an upper surface of the structure and electrically connects with at least one other region having the first conductivity type formed in the active region. A buried well having a second conductivity type is formed in the active region and is coupled with a second terminal formed on the upper surface of the structure. The buried well and the active region form a clamping diode which positions a breakdown avalanche region between the buried well and the first terminal. A breakdown voltage of at least one of the power devices is a function of characteristics of the buried well.