Power Die PCB Via Layout for Thermal Stress Reliability
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Solution Overview
Problem
The reliability of connections between power semiconductor dies and PCBs is compromised by thermal expansion coefficient mismatches, leading to mechanical stress, fatigue damage, and delamination due to non-uniform temperature distribution, which accelerates deterioration in hotter regions.
Innovation Solution
A power module design with vias arranged in a decreasing density pattern from the hot spot to the peripheral area, combined with a cavity filled with conductive material, to redistribute thermal stress and improve temperature homogeneity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If vias are arranged with uniform density on the PCB, then the manufacturing process is simple, but the hotter regions suffer from premature deterioration due to thermal stress concentration
Solution Approach 1:
The patent applies local quality by varying the via density according to the temperature distribution on the semiconductor die. Higher via density is placed in cooler peripheral regions while lower via density is placed in the hotter central region. This non-uniform distribution optimizes thermal stress distribution and prevents premature deterioration in hot spots, resolving the contradiction between manufacturing simplicity and connection reliability.
2Temperature
If via density is increased to improve thermal connection, then thermal resistance decreases, but mechanical stress and fatigue damage increase due to CTE mismatch
Solution Approach 1:
The patent resolves this contradiction by applying local quality through spatially varying via density. The via density is locally optimized to match the temperature distribution - higher density in cooler areas for better thermal connection, and lower density in hotter areas to reduce thermal stress concentration. This balanced approach improves overall thermal connection while preventing mechanical failure in critical hot regions.
3Strength
If via density is decreased to reduce thermal stress, then fatigue damage decreases, but thermal resistance increases
Solution Approach 1:
The patent resolves this contradiction through local quality by implementing a non-uniform via density distribution that matches the temperature profile of the semiconductor die. Cooler peripheral regions maintain higher via density for effective thermal management, while the hotter central region uses lower via density to minimize thermal stress and fatigue damage. This spatial optimization achieves both low thermal resistance and high fatigue resistance simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the mechanical, electrical, and thermal joining, reducing thermal resistance and fatigue, thereby increasing the lifetime and reliability of the connection.
Implementation Method 1
vias filled with conductive material to provide connecting pads between said metallized connection surface of said die and said conductive path
Implementation Method 2
mechanical stress due to unmatched thermal expansion characteristics will lead to fatigue damage and consequently delamination of the PCB
Data Source
AI summary
Power module comprising a power semiconductor die and at least one substrate comprising an insulating layer in contact with a metallized connection surface of said die and at least one conductive path on a conductive layer on a face of the insulating layer opposite to the metallized connection surface of the die and wherein said insulating layer comprises vias filled with conductive material to provide connecting pads between said metallized connection surface of said die and said conductive path, and wherein said vias are arranged with a decreasing density from at least one hot spot position of said metallized connection surface when the die is in operation to a peripheral area of said metallized connection surface.