Power-Down Exit Timing in Semiconductor Input Buffer Circuits
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Solution Overview
Problem
Existing semiconductor devices face issues with undesired signals being erroneously decoded during power down and power up transitions, affecting reliability, particularly in deep power down modes.
Innovation Solution
A semiconductor device design that converts the logic level of the power down exit signal at the falling edge of the chip selection signal, enabling the input buffer circuit to transmit signals only after a controlled delay, thereby preventing erroneous command decoding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the logic level of the power down exit signal is converted at the first edge (rising edge) of the chip selection signal, then the device can quickly respond to power down commands, but undesired signals are erroneously decoded during power transitions
Solution Approach 1:
The patent applies preliminary action by converting the logic level of the power down exit signal at the second edge (falling edge) of the chip selection signal before the input buffer circuit is fully activated. This timing sequence ensures that the power down exit signal is ready in advance, allowing the input buffer circuit to properly receive and process signals without erroneous decoding, thus resolving the contradiction between quick response and signal accuracy
Solution Approach 2:
The patent uses the chip selection signal as an intermediary to control the timing of the power down exit signal conversion. By leveraging the edge transitions of the chip selection signal, the system coordinates the activation of the power down exit signal with the input buffer circuit's operational state, preventing erroneous decoding while maintaining reliable signal transmission
2Productivity
If the input buffer circuit transmits signals immediately upon power restoration, then the device recovers quickly from power down mode, but erroneous commands are decoded due to timing issues
Solution Approach 1:
The patent applies preliminary action by preparing the power down exit signal conversion at the second edge of the chip selection signal before the input buffer circuit activates. This ensures that the control signal is ready in advance, allowing the input buffer circuit to recover quickly while avoiding erroneous command decoding through proper timing coordination
Solution Approach 2:
The patent implements feedback by using the chip selection signal's edge transitions to control the power down exit signal conversion timing. The system monitors the chip selection signal state and adjusts the power down exit signal accordingly, creating a feedback mechanism that prevents erroneous decoding while maintaining fast recovery
Data Source
AI summary
A semiconductor device includes: a power down control circuit receiving a power down command signal and a chip selection signal, and generating a power down enable signal and a power down exit signal, here, a logic level of the power down enable signal is converted at a first edge of the power down command signal during a power down stage, and a logic level of the power down exit signal is converted at a second edge of the chip selection signal during a power down exit stage; a power control circuit stopping providing a power voltage according to the power down enable signal during the power down stage, and providing the power voltage according to the power down exit signal during the power down exit stage; and an input buffer circuit transmitting signals during the power down exit stage in response to the power down exit signal.