Power Gating Cell Topology for Retention Voltage and Leakage Control
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Solution Overview
Problem
Current integrated circuits face challenges in efficiently managing power consumption and leakage current, particularly in sleep modes, as existing power gating circuits do not effectively provide retention voltages and power-off states, leading to inefficiencies in logic circuit block operations.
Innovation Solution
The integration of a power gating circuit with a PMOS and NMOS transistor configuration, allowing for the generation of various retention voltages and power modes by selectively connecting power lines to virtual power lines through control signals, enabling efficient power management and reduced leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If power gating circuit blocks power supply to logic circuit block in sleep mode, then leakage current is reduced, but retention voltage cannot be provided to maintain internal state
Solution Approach 1:
The power supply network is segmented into multiple paths: a first power line connected to a first transistor for blocking power supply to reduce leakage, and a second power line connected to a second transistor for providing retention voltage. This segmentation allows independent control of power blocking and state retention functions.
Solution Approach 2:
A retention voltage line is introduced as an intermediary power supply path that can provide a different voltage level than the main power line. This intermediary path enables the logic circuit block to maintain its internal state with a reduced retention voltage while the main power line is blocked to minimize leakage current.
2Reliability
If power gating circuit provides retention mode with retention voltage, then internal state is maintained, but power consumption is not sufficiently reduced
Solution Approach 1:
The voltage level parameter is changed by providing a retention voltage that is different from (and lower than) the operation voltage. This parameter change allows the circuit to maintain functionality at a reduced voltage level, thereby reducing power consumption while preserving the internal state.
3Loss of energy
If power gating circuit uses simple transistor switching, then power supply is blocked effectively, but multiple power modes cannot be provided
Solution Approach 1:
The power gating circuit is made dynamic by introducing multiple controllable transistors (first transistor on first power line, second transistor on second power line) that can be independently controlled. This dynamic configuration allows the circuit to switch between different power modes (power-on mode, retention mode, power-off mode) based on operational requirements.
Data Source
AI summary
An integrated circuit is provided. The integrated circuit includes a power gating circuit configured to receive a power supply voltage from a first power line and to output a first driving voltage to a first virtual power line and a logic circuit electrically connected to the first virtual power line and configured to receive power from the power gating circuit. The power gating circuit includes a first p-type transistor and a first n-type transistor connected in parallel between the first power line and the first virtual power line.