Power Ground Network Segmentation for IC Layout Efficiency
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Solution Overview
Problem
Current power/ground (P/G) network designs in integrated circuits are inefficient, leading to insufficient interconnection resources, increased costs, and timing issues due to inadequate consideration of standard cell sizes and power/ground widths, resulting in IR drop and other problems.
Innovation Solution
A novel P/G network arrangement where horizontal and vertical metal stripes are strategically placed in different metal layers, with horizontal power metal stripes covering only power lines and horizontal ground metal stripes covering only ground lines, ensuring optimal width and spacing to prevent overlapping and improve power delivery, calculated based on factors like IR drop, power consumption, noise, and design rules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the width of metal stripes in P/G network is increased to cover both power and ground lines, then connection reliability is improved, but layout resource efficiency deteriorates and P/G short risk increases
Solution Approach 1:
The patent segments the metal stripe width into two distinct types: first metal stripes with width covering only power lines (or only ground lines), and second metal stripes with width covering both power and ground lines. This segmentation allows different regions of the P/G network to use appropriately sized metal stripes, improving overall layout efficiency while maintaining connection reliability where needed.
Solution Approach 2:
The patent applies different metal stripe widths to different locations based on local requirements. First metal stripes with narrower width are used in regions where only single-line coverage is needed, while second metal stripes with wider coverage are used where both power and ground lines require connection. This local differentiation optimizes resource usage while ensuring connection reliability.
2Quantity of substance
If chip area is enlarged to provide more interconnection resources, then P/G network capacity is improved, but cost and timing performance deteriorate
Solution Approach 1:
The patent changes the parameter of metal stripe width to optimize interconnection resource usage. By using first metal stripes with width equal to or greater than the maximum width of single power/ground lines, and second metal stripes with width equal to or greater than the sum of power and ground line widths, the patent provides adequate interconnection capacity without unnecessarily enlarging chip area, thereby controlling manufacturing cost.
3Power
If metal stripe width is increased to ensure adequate power delivery, then power supply capability is improved, but IR drop and noise performance deteriorate
Solution Approach 1:
The patent segments power delivery paths into regions served by first metal stripes and regions served by second metal stripes. This segmentation creates dedicated power and ground paths that reduce current crowding and minimize IR drop, while the structured arrangement reduces electromagnetic noise coupling.
Data Source
AI summary
An arrangement scheme for a power/ground (P/G) network of an integrated circuit is provided. Rows of standard cells in the integrated circuit are horizontally arranged. The P/G network has horizontal and vertical metal lines arranged in different metal layers. The horizontal metal lines have horizontal power metal lines and horizontal ground lines. The vertical metal lines have vertical power metal lines and vertical ground lines. The power lines and the ground lines in the horizontal metal lines are respectively interconnected with the power lines and the ground lines of the vertical metal lines. The width of the horizontal metal wires in the P/G network is such that the horizontal power metal lines only cover the power lines in the rows of the standard cells, while the horizontal ground metal lines only cover the ground lines of the rows of the standard cells. By employing the technical features of the present invention compliant with the conditions of IR drop, power consumption and noise, the P/G network is rearranged and the metal line width can be determined based on the design rules for integrated circuit and the repeatability of the rows of the standard cells, thus avoiding function failure or waste of layout resources due to overlapping or inappropriate line width, thereby accommodating the requirement for chip designs.