Power and Ground Pin Testing via Segmented Resistor Networks
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current methods fail to effectively test the integrity of individual power and ground pins on semiconductor integrated circuits, leading to potential operational failures due to poor wire bonds and manual inspection inefficiencies.
Innovation Solution
Organizing power pins into groups connected through resistors to common nodes, applying voltage, and using comparators to identify defective pins based on threshold voltage comparisons.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If manual inspection methods are used to test wire bonds, then the testing process is simple, but the inspection is slow and imprecise
Solution Approach 1:
The patent replaces manual mechanical inspection with an automated electrical testing system. The test circuit applies voltage through resistors to power pins and uses comparators to automatically detect voltage deviations, enabling both high precision and speed without human intervention.
Solution Approach 2:
The testing circuit is integrated into the chip itself, using the chip's own power pins and internal circuitry to perform self-diagnosis. The comparators and resistors form an autonomous testing system that can identify defective pins without external testing equipment.
2Adaptability or versatility
If existing electrical test methods using ESD circuitry are used, then individual signal pins can be tested, but power and ground pins cannot be effectively tested
Solution Approach 1:
The patent segments the power pins into multiple groups, with each group connected to a separate comparator through a dedicated resistor. This segmentation allows independent testing of each power pin's integrity, enabling reliable detection of defective power and ground pins that were previously untestable.
Solution Approach 2:
The testing circuit is designed to universally test all types of pins including power pins, ground pins, and signal pins. By using the same comparator-based architecture for all pin types, the system achieves comprehensive coverage without requiring separate testing methods for different pin categories.
3Reliability
If wire bonding process is used to connect pads to lead frame, then electrical connections are formed, but poor bonds, breaks, and damage occur due to misalignment, pressure issues, and contaminants
Solution Approach 1:
The patent implements preliminary electrical testing of power and ground pins before final packaging and delivery. By using the integrated test circuit with comparators and resistors, defects can be detected early in the manufacturing process, allowing for rework or rejection of defective units before they cause field failures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method allows for precise and efficient identification of bad power and ground pins, ensuring proper voltage distribution and chip functionality, overcoming the limitations of existing testing methods.
Implementation Method 1
The voltage at each of the first group of pins is compared with a first threshold voltage and the voltage at each of the second group of pins is compared with a second threshold voltage
Data Source
AI summary
To achieve the foregoing, and in accordance with the purpose of the present invention, a method and apparatus for testing individual power and ground pins on a semiconductor integrated circuit are disclosed. The method and apparatus includes organizing the power pins of the die into a first group of power pins and a second group of power pins. Each of the first group of power pins are then connected through a first set of resistors to a first common node, and each of the second group of power pins through a second set of resistors to a second common node respectively. A voltage is next applied between the first and second nodes. The voltage at each of the first group of pins is compared with a first threshold voltage and the voltage at each of the second group of pins is compared with a second threshold voltage. Individual bad pins in the first and second groups are identified based on the comparison.