Power IO Cell Layout for Higher ESD Tolerance in ICs
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Solution Overview
Problem
The increase in wiring resistance and lower power supply voltages in semiconductor integrated circuits leads to decreased electrostatic discharge (ESD) tolerance, and existing solutions to improve ESD tolerance, such as connecting power supply lines, result in increased area requirements.
Innovation Solution
A semiconductor integrated circuit device configuration with IO cells that includes power IO cells having external terminals connected to ESD protection devices between power supplies, and power supply lines extending in a specific direction, allowing for reduced resistance without increasing the device's area by overlapping external terminals with power supply lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power supply lines are mutually connected in IO cells and inner circuits to strengthen power supply lines, then ESD tolerance is improved, but the area of the semiconductor integrated circuit device increases
Solution Approach 1:
The patent utilizes the vertical dimension by allowing external terminals to overlap with power supply lines in the second direction (vertical to the first direction). This dimensional approach enables the second external terminal to be positioned without increasing the planar area, while still maintaining electrical connection through the overlapping region. The ESD protection device is formed in the region between external terminals, utilizing the vertical stacking to achieve both ESD protection and area efficiency.
Solution Approach 2:
The patent merges the function of external terminals with power supply lines by allowing them to overlap and share the same spatial region. The second external terminal is placed at a position having an overlap with one of the power supply lines, effectively combining the terminal function with the power distribution network. This merging eliminates the need for separate dedicated terminal areas, thus preventing area increase while maintaining ESD protection capability.
2Reliability
If wiring resistance is reduced by improving power supply line configuration, then ESD tolerance is improved, but device area increases due to additional wiring resources
Solution Approach 1:
The patent makes the power supply lines serve multiple functions: they simultaneously act as power distribution conductors and as spatial references for positioning external terminals. The power supply lines in the first direction serve both to supply power to the core region and to define the vertical positioning of external terminals through overlap. This multi-functionality eliminates the need for separate dedicated terminal wiring, reducing total wiring resources while maintaining low resistance paths for ESD protection.
Solution Approach 2:
By transitioning to vertical overlap positioning, the patent eliminates the need for horizontal separation between terminals and power lines. The second external terminal overlaps with power supply lines in the vertical direction, allowing the same wiring structure to serve both power distribution and terminal connection purposes without requiring additional horizontal wiring resources.
Data Source
AI summary
In an IO region of a semiconductor integrated circuit device, placed is an IO cell row including a signal IO cell and a power IO cell supplying a first power supply. The power IO cell includes first and second external terminals connected to an external connection pad and an electrostatic discharge (ESD) protection device formed at least in a region between the first and second external terminals. The first external terminal is placed at a position having an overlap in the Y direction with a power supply line for a second power supply.