Power Management Unit State Machine for Low Power Modes
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Solution Overview
Problem
Conventional power management units in mobile devices lack the ability to control voltage sources during low power modes and are inflexible, lacking programmability and security, which limits their ability to manage and transition between different power modes independently of the main CPU.
Innovation Solution
A self-contained power management unit with a state machine and dynamic register sets that allows independent control of voltage levels and transitions between RUN, HIBERNATE, and POWERDOWN modes, using a control interface and external power sources, and can be implemented in hardware, software, or a combination of both, with built-in security and adaptability to various power management units and communication protocols.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the device is put into hibernate or powerdown modes to save battery power, then power consumption is reduced, but the capability to perform operations and functions is lost
Solution Approach 1:
The power management unit is segmented into multiple independent voltage domains (first voltage domain and second voltage domain) that can be controlled separately. This allows the CPU to operate at full voltage while peripheral devices operate at reduced voltage, enabling operations to continue while reducing overall power consumption.
Solution Approach 2:
The system dynamically adjusts voltage levels in different domains based on operational requirements. The first voltage domain maintains higher voltage for CPU operations, while the second voltage domain operates at lower voltage for peripheral devices, allowing the system to adapt power consumption to actual operational needs.
2Ease of operation
If conventional power management units are used, then device operation is simplified, but flexibility and programmability are reduced
Solution Approach 1:
The power management unit is designed with universal control capabilities that can manage multiple voltage domains and support various operational modes. The control logic can programmatically adjust voltage levels across different domains, providing both ease of operation through automated management and flexibility through programmable control.
Solution Approach 2:
The power management unit acts as an intermediary between the CPU and peripheral devices, mediating voltage supply and power control. This intermediary can be programmed to implement complex power management strategies while presenting a simplified interface to both the CPU and peripheral devices.
3Use of energy by moving object
If voltage is reduced to zero or very low levels to save power, then power consumption is minimized, but the ability to transition between voltage levels and resume operations is lost
Solution Approach 1:
The control logic is pre-programmed with the sequence and parameters for voltage transitions. When a wake-up event occurs, the system automatically executes the pre-planned voltage restoration sequence, first restoring peripheral devices and then the CPU, eliminating the need for complex real-time decision-making during wake-up.
Solution Approach 2:
The power management unit incorporates feedback mechanisms that monitor the state of voltage domains and automatically adjust voltage levels accordingly. This feedback system ensures that voltage transitions occur at the appropriate times and that the system can reliably resume operations without manual intervention.
Data Source
AI summary
A state machine and an external interface, including its associated input-outputs (IOs), are always powered on and used to manage the chip power modes and power mode transitions. The chip power modes are defined as RUN, HIBERNATE, POWERDOWN, with many more possible with this invention. For example, once the device is in HIBERNATE or POWERDOWN modes, the power supplies to the IC are either reduced, or completely disconnected except for this controller state machine. This invention's state machine and control mechanism, in response to some external “wake up event”, will bring the chip to RUN mode by managing the state of the external power supplies through its control interface. The implementation achieves small die size and extreme low power consumption.