Power Mesh-On-Die Solder Trace Bumping
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Solution Overview
Problem
The challenge in miniaturized semiconductor packages is to maintain high current capacity while reducing resistance in power and ground wiring to support increasing performance demands without increasing the size of the wiring dimensions.
Innovation Solution
The implementation of a power mesh-on-die technology that uses channeled solder between power or ground bumps to enhance electrical capacity, where the solder mask is opened above trace wiring to create solder-enhanced traces between adjacent bumps, allowing solder to flow and form a trace between bumps, thereby reducing resistance and improving electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If wiring dimensions are reduced for miniaturization, then package size is reduced, but electrical resistance increases and current capacity decreases
Solution Approach 1:
The patent applies composite materials by combining copper trace wiring with solder material to create a hybrid power distribution structure. The copper trace provides baseline electrical connectivity, while the solder bump and wick material enhance current capacity and reduce resistance. This composite approach allows miniaturization while maintaining electrical performance by leveraging the complementary properties of different materials.
Solution Approach 2:
The patent transitions from two-dimensional planar wiring to three-dimensional vertical structures by adding solder bumps and wick paths. The power delivery network extends into the vertical dimension with solder bumps rising from the substrate, creating multiple conductive pathways and increasing effective wiring cross-section without increasing package footprint, thereby reducing resistance while maintaining compact size.
2Reliability
If wiring cross-section is increased to reduce resistance, then current capacity improves, but package area increases
Solution Approach 1:
The patent resolves this contradiction by moving conductive material into the vertical dimension. Solder bumps provide additional conductive cross-section perpendicular to the substrate plane, increasing current capacity without expanding the horizontal wiring area. The wick structure extends vertically from the trace to the bump, creating a three-dimensional conductive pathway that enhances current handling while maintaining compact package footprint.
Solution Approach 2:
The patent applies local quality by concentrating enhanced conductivity where needed - at the power bumps and along the trace paths between them. The solder mask is selectively removed only in channels above the traces, and solder is applied only at bump locations and trace channels, creating localized high-conductivity regions that improve current capacity without requiring uniform increase in overall wiring area.
3Reliability
If more solder material is used to enhance traces, then electrical resistance decreases, but manufacturing complexity increases
Solution Approach 1:
The patent employs self-service through capillary action, where the wick structure automatically draws solder from the bump to the trace during the reflow process. This self-wicking mechanism eliminates the need for complex external dispensing systems or manual solder placement, allowing the structure to self-assemble the enhanced conductive pathway through passive capillary forces during standard reflow processing.
Solution Approach 2:
The solder mask channel acts as an intermediary structure that guides and controls solder flow. By creating a defined channel in the solder mask above the trace, the patent provides a controlled pathway that directs solder from the bump to the trace, simplifying the manufacturing process compared to attempting to directly deposit solder onto the trace without such a guiding structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively lowers electrical resistance, enabling higher current capacity and faster switching speeds while managing noise levels, thus preventing functional failures in high-power conditions without increasing the physical dimensions of the wiring.
Implementation Method 1
The implementation of a power mesh-on-die technology that uses channeled solder between power or ground bumps to enhance electrical capacity
Implementation Method 2
channeled solder between power or ground bumps to enhance electrical capacity, where the solder mask is opened above trace wiring to create solder-enhanced traces between adjacent bumps, allowing solder to flow and form a trace between bumps, thereby reducing resistance
Data Source
AI summary
A power mesh-on-die apparatus includes a solder trace that enhances current flow for a power source trace between adjacent power bumps. The solder trace is also applied between power drain bumps on a power drain trace.