Power-Mode-Aware Clock Tree for Multi-Voltage Skew Control
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Solution Overview
Problem
Conventional clock trees in integrated circuits (ICs) fail to maintain optimal clock skew across different power modes due to varying operating voltages, leading to increased clock skew and area costs associated with additional synchronization circuits.
Innovation Solution
A power-mode-aware (PMA) clock tree with sub clock trees and PMA buffers that adjust delay times based on power information to optimize clock signal delivery across different power modes, reducing clock skew while minimizing area costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the operating voltage of a function module is turned down to reduce power consumption, then power consumption is reduced, but clock skew increases due to increased clock delay
Solution Approach 1:
The patent implements dynamic delay adjustment in clock buffers based on detected power modes. The system transitions from static clock buffering to dynamic buffering where delay characteristics are adjusted in real-time according to the operating power mode, resolving the contradiction between power savings and clock skew control
Solution Approach 2:
The patent changes the delay parameter of clock buffers based on power mode detection. By detecting the power mode and correspondingly adjusting the delay parameter of clock buffers, the system maintains optimal clock skew across different power consumption levels without requiring additional synchronization circuits
2Reliability
If asynchronous design is adopted to achieve clock synchronization across power modes, then clock synchronization is achieved, but system complexity increases due to handshake protocols and additional synchronization circuits
Solution Approach 1:
The patent implements a self-service mechanism where the clock tree system automatically detects power modes and adjusts buffer delays without external intervention. This eliminates the need for complex handshake protocols and additional synchronization circuits required by asynchronous design approaches
Solution Approach 2:
The patent introduces feedback mechanisms where power mode detection information is fed back to clock buffers, enabling automatic delay adjustment. This feedback loop replaces complex asynchronous synchronization protocols with a simpler, automated control mechanism
3Reliability
If adjustable delay buffer or delay locked loop is adopted to synchronize clock signals, then clock skew is optimized, but area cost increases due to additional circuits and reference clock requirements
Solution Approach 1:
The patent makes existing clock buffers multi-functional by enabling them to operate in different delay modes based on power mode detection. This eliminates the need for separate adjustable delay buffers or delay locked loops, achieving clock skew optimization without additional area cost
Solution Approach 2:
The patent uses power mode detection information as a virtual copy of timing requirements to control buffer delays. Instead of physically copying synchronization circuits for each power mode, the system uses information-based control to achieve the same effect with minimal area overhead
Data Source
AI summary
A power-mode-aware (PMA) clock tree and a synthesis method thereof are provided. The clock tree includes a sub clock tree and a PMA buffer. The sub clock tree transmits a delayed clock signal to a function module, wherein a power mode of the function module is determined according to a power information. The PMA buffer is coupled to the sub clock tree. The PMA buffer determines the delay time of a system clock signal according to the power information delays the system clock signal, and outputs the delayed system clock signal to the sub clock tree as the delayed clock signal.