Power Module Alternating Contact Surfaces Reduce Parasitic Induction
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Solution Overview
Problem
Power output stages in hybrid electric/electric vehicles experience parasitic induction currents due to the physical properties of power transistors, leading to faults and failures.
Innovation Solution
The use of multiple smaller power transistors instead of single large ones, with alternating electrical connections and busbars, reduces the total induction area and intensity of parasitic currents, and the configuration of contact surfaces and busbars minimizes induction areas between positive and negative voltage sides.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If single large power transistors are used to provide high current, then the current handling capability is improved, but parasitic induction currents increase causing faults and failures
Solution Approach 1:
The patent divides a single large power transistor into multiple smaller power transistors (e.g., four transistors instead of one). This segmentation reduces the loop area for parasitic induction currents while maintaining the same total current handling capability. Each smaller transistor processes a portion of the total current, and their combined effect achieves the required power output without the harmful parasitic effects of a single large transistor.
2Reliability
If multiple power transistors are used to reduce parasitic currents, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent combines multiple power transistors and their associated contact areas into an integrated power module structure. The circuit carrier integrates multiple first contact areas, second contact areas, and third contact areas with multiple power transistors in a unified design. This merging approach manages the complexity by creating a standardized modular structure that, while more complex internally, provides improved reliability through the distributed transistor architecture.
3Object-generated harmful factors
If alternating contact areas are used to reduce induction areas, then parasitic current reduction is improved, but manufacturing complexity increases
Solution Approach 1:
The patent applies different contact area configurations to different regions of the circuit carrier. First contact areas are positioned for positive voltage connections, second contact areas for negative voltage connections, and third contact areas for alternating connections. This local differentiation of contact area qualities optimizes the reduction of induction areas in specific regions while maintaining a systematic manufacturing approach through standardized placement patterns.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly reduces parasitic induction currents, enhancing the reliability and efficiency of power output stages by minimizing induction areas and allowing for easier maintenance and production.
Implementation Method 1
Power transistors which, controlled by external control signals, transfer phase currents with currents of up to several hundred or even more than 500 amperes to a downstream high-power load
Implementation Method 2
Due to the physical properties of the power output stages or the power transistors in the power output stages, parasitic induction currents arise in the power output stages
Data Source
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AI summary
A power module (LM, LM') is disclosed, comprising: a circuit carrier (ST) which has an interface (OF); at least two first contact surfaces (KF11, KF12) are arranged on the interface (OF), on which first contact surfaces first power transistors (T11, T12) are respectively directly arranged and connected in an electrically conductive manner to the respective first contact surfaces (KF11, KF12) via a ground contact surface; a second contact surface (KF2) is arranged on the interface (OF), on which second contact surface at least two second power transistors (T21, T22) are arranged and are each connected in an electrically conductive manner to the second contact surface (KF2) via a ground contact surface; at least two third contact surfaces (KF31, KF32) are arranged on the interface (OF), wherein the at least two second power transistors (T21, T22) are each connected in an electrically conductive manner to one of the at least two third contact surfaces (KF31, KF32) via an additional contact surface (S21, S22); wherein the at least two first contact surfaces (KF11, KF12) and the at least two third contact surfaces (KF31, KF32) are arranged alternatingly one after the other in a direction (LR), and the second contact surface (KF2) is arranged next to the at least two first contact surfaces (KF11, KF12) and next to the at least two third contact surfaces (KF31, KF32).