Power Semiconductor Module Layout With Chiral Chip Metallization
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Solution Overview
Problem
Existing power semiconductor module arrangements face damage to chip metallizations during the formation of electrical connections due to the use of tools, which can unintentionally scratch or damage other structures on the semiconductor elements.
Innovation Solution
The layout of chip metallizations on the semiconductor dies is designed in chiral patterns, with specific arrangements of metallizations on the top surface to minimize the risk of damage during the formation of electrical connections, using a common layout for multiple semiconductor dies to reduce tool interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If tools are used to form electrical connections between chip metallizations, then electrical connections are established, but the tools may unintentionally damage other chip metallizations
Solution Approach 1:
The patent applies asymmetry by using chiral (non-superimposable mirror image) patterns for chip metallizations. Each pattern is designed with asymmetric geometry that prevents tool-induced damage by ensuring that tools approaching from any direction will first encounter the pattern's outer boundaries rather than internal metallization structures. This asymmetric design makes the metallization patterns inherently resistant to accidental tool contact damage during electrical connection formation.
Solution Approach 2:
The patent implements preliminary anti-action by pre-designing the chip metallization patterns with protective geometric features before the electrical connection formation process. The chiral patterns are configured in advance to create protective zones and directional approach characteristics that preemptively prevent tool damage. This preliminary design ensures that even if tools are not perfectly positioned, the asymmetric geometry will naturally guide tools away from sensitive internal structures.
2Device complexity
If standard metallization patterns are used on semiconductor dies, then manufacturing is simplified, but tools may accidentally contact and damage internal chip metallizations during connection formation
Solution Approach 1:
The patent resolves this contradiction by introducing chiral asymmetric patterns that maintain manufacturing feasibility while significantly improving reliability. The asymmetric design is implemented using standard fabrication processes, and the patterns can be replicated across multiple dies. The key advantage is that the asymmetric geometry provides inherent protection without requiring complex additional manufacturing steps, thus maintaining acceptable device complexity while dramatically improving metallization integrity.
Solution Approach 2:
The patent applies parameter changes by modifying the geometric parameters of the chip metallization patterns. Specifically, the patterns are designed with optimized dimensions, spacing, and angular orientations that create protective characteristics. By carefully selecting and adjusting these geometric parameters, the patent achieves both manufacturing simplicity and enhanced protection against tool-induced damage.
Data Source
Figure 1~2
Figure 3~4B
Figure 5~6B
AI summary
A power semiconductor module arrangement (200) comprises a substrate (10) comprising a dielectric insulation layer (11), and a first metallization layer (111) arranged on a first side of the dielectric insulation layer (11), at least one first semiconductor die (24) implemented as a switching device and mounted on the first metallization layer (111) of the substrate (10), and at least one second semiconductor die (26) implemented as a switching device and mounted on the first metallization layer (111) of the substrate (10). Each of the at least one first semiconductor die (24) comprises a first chip metallization (241), a second chip metallization (242) and a third chip metallization (243) arranged on a top side of the respective first semiconductor die (24), wherein a top side of a first semiconductor die (24) is a side of the first semiconductor die (24) that faces away from the substrate (10), each of the at least one second semiconductor die (26) comprises a first chip metallization (26i), a second chip metallization (262) and a third chip metallization (263) arranged on a top side of the respective second semiconductor die (26), wherein a top side of a second semiconductor die (26) is a side of the second semiconductor die (26) that faces away from the substrate (10), the first chip metallization (241), the second chip metallization (242) and the third chip metallization (243) of each of the at least one first semiconductor die (24) form a first pattern on the top side of the respective first semiconductor die (24), the first chip metallization (261), the second chip metallization (262) and the third chip metallization (263) of each of the at least one second semiconductor die (26) form a second pattern on the top side of the respective second semiconductor die (26), the second pattern being different from the first pattern, and the first pattern and the second pattern are chiral patterns.