Power Module Interposer Stacking for Parasitic Inductance Reduction
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Solution Overview
Problem
Conventional semiconductor devices, such as discrete power semiconductor devices like IGBTs, face issues with high overshoot voltage due to parasitic inductance and poor heat dissipation, leading to reduced efficiency and reliability.
Innovation Solution
The integration of a power module with an internal interposer and opposing substrates, which includes a core substrate with conductive vias for vertical electrical interconnects and thermally conductive materials for effective heat dissipation, along with specific patterns of interconnect pads for accurate alignment and reduced parasitic effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional discrete power semiconductor devices are used, then device simplicity is maintained, but parasitic inductance causes high overshoot voltage and poor heat dissipation
Solution Approach 1:
The patent transitions from planar interconnect布局 to three-dimensional vertical stacking architecture. Multiple power semiconductor devices are stacked vertically with interconnect structures extending through multiple layers, transforming the traditional two-dimensional layout into a three-dimensional configuration that reduces signal path length and parasitic inductance while improving heat dissipation through vertical thermal pathways
Solution Approach 2:
The patent implements nested interconnect structures where conductive pathways are embedded within multiple substrate layers. Interconnect structures are nested between stacked semiconductor devices, with conductive vias and traces integrated within the substrate thickness, creating a compact nested architecture that minimizes external parasitic inductance
2Temperature
If conventional substrate configurations are used, then manufacturing simplicity is maintained, but heat dissipation efficiency is poor
Solution Approach 1:
The patent divides the substrate into multiple stacked layers, each serving specific functions for heat management. The substrate is segmented into first and second substrates with intermediate interconnect layers, creating distinct thermal zones and pathways that enable efficient heat dissipation from each semiconductor device to dedicated heat sink areas in the substrate
Solution Approach 2:
The patent introduces intermediate interconnect structures and thermal interface materials between stacked semiconductor devices and substrate heat sink areas. These intermediary layers facilitate efficient thermal transfer while maintaining electrical isolation where needed, acting as mediators that improve heat dissipation without requiring direct contact between devices and substrate
3Ease of operation
If longer signal paths are used in conventional devices, then routing flexibility is improved, but electrical parasitic effects increase
Solution Approach 1:
The patent utilizes vertical routing through multiple substrate layers to achieve compact signal paths. Instead of lateral routing that consumes space and increases parasitics, signals are routed vertically through conductive vias and traces embedded in the stacked substrate structure, dramatically reducing signal path length while maintaining routing flexibility through three-dimensional interconnect design
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces signal path length, minimizes electrical parasitic effects, and enhances heat dissipation, resulting in improved efficiency, reliability, and reduced operating temperatures of semiconductor devices.
Implementation Method 1
core substrate with conductive vias for vertical electrical interconnects and thermally conductive materials for effective heat dissipation
Data Source
AI summary
A semiconductor device has an interposer including a plurality of conductive vias formed through the interposer. A first semiconductor die is disposed over the interposer. A second semiconductor die is disposed over a first substrate. The first semiconductor die and second semiconductor die are power semiconductor devices. The interposer is disposed over the second semiconductor die opposite the first substrate. A second substrate is disposed over the first semiconductor die opposite the interposer. The first substrate and second substrate provide heat dissipation from the first semiconductor die and second semiconductor die from opposite sides of the semiconductor device. A plurality of first and second interconnect pads is formed in a pattern over the first semiconductor die and second semiconductor die. The second interconnect pads have a different area than the first interconnect pads to aid with alignment when stacking the assembly.