Power Semiconductor Package Layout for Balanced Parallel Die Switching
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Solution Overview
Problem
Existing power semiconductor device packages face issues with desynchronized switching and imbalanced current due to differing electrical impedances in parallel dies, inefficient space utilization, and inadequate electromagnetic interference (EMI) shielding, particularly with high-frequency signals.
Innovation Solution
A package structure with a substrate featuring semiconductor dies connected via bonding components, where the gate control conductive trace is connected to each die and sandwiched between circuit lines formed by power switching pads, and a Kelvin conductive trace is used to enclose or be enclosed by the gate control trace, ensuring balanced impedances and improved EMI shielding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the gate control conductive trace is located on the lower part of the semiconductor substrate, then the connection is established, but the trace occupies almost all of the lower part portion, resulting in low space utilization rate
Solution Approach 1:
The gate control conductive trace is moved from the lower part of the substrate to the upper part, utilizing a different spatial dimension. This dimensional relocation allows the lower substrate area to be used for other purposes (such as temperature sensor placement), thereby increasing overall space utilization while maintaining the electrical connection function
2Reliability
If parallel power semiconductor dies are connected with different control loop lengths, then the connection is established, but the electrical impedances differ, causing desynchronized switching or imbalanced current
Solution Approach 1:
The patent designs the control loops for parallel semiconductor dies to have equal lengths, creating equipotential conditions for signal propagation. This ensures that all parallel dies experience the same electrical impedance and timing characteristics, thereby achieving synchronized switching and balanced current distribution without complex adjustment mechanisms
3Power
If high frequency signals are used in semiconductor dies, then the power control capability is enhanced, but signal integrity and electromagnetic wave shielding problems occur, leading to poor EMI characteristics
Solution Approach 1:
The patent converts the harmful electromagnetic emissions into beneficial effects by implementing a shielding structure where the source contact and drain contact are positioned to create an electromagnetic shield. This configuration uses the high-frequency signals themselves to generate opposing electromagnetic fields that cancel out external interference, thereby improving EMI characteristics while maintaining high power control capability
Data Source
AI summary
A package structure for a power semiconductor device is provided, including: a substrate; two or more semiconductor dies on the substrate, each of the semiconductor dies includes a first power switching pad, a second power switching pad and a gate; a gate control conductive trace, a first power switching contact and a second power switching contact are further arranged on the substrate, the gate control conductive trace is connected to each of the semiconductor dies via a bonding component, and the bonding component connecting a first semiconductor die to the gate control conductive trace is sandwiched between circuit lines formed by connecting the second power switching pads of the first semiconductor die and the neighboring second semiconductor die, to second power switching contact of the substrate.