Power Semiconductor Package Layout for Low-Parasitic Motor Drivers
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Solution Overview
Problem
The relative arrangement of contact regions on power semiconductor chips and external terminals in semiconductor packages can lead to increased parasitic resistances and inductances, which are problematic for applications such as drivers for electric motors.
Innovation Solution
The semiconductor package design minimizes the length and number of electrical connections by strategically arranging external terminals and contact regions, using a configuration that allows for closer bonding points and reduces parasitic resistances and inductances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the electrical connections between contact regions and external terminals are made longer to accommodate terminal arrangements, then the ease of manufacture and assembly is improved, but the parasitic resistances and inductances increase
Solution Approach 1:
The patent transitions from planar arrangement of contacts and terminals to a three-dimensional vertical arrangement. Multiple external terminals are positioned at different heights above the semiconductor chip, with bonding wires connecting vertically to contact regions on the chip surface. This vertical dimensionality allows terminals to be arranged for ease of assembly while maintaining short electrical connection lengths, thereby reducing parasitic effects.
Solution Approach 2:
The patent employs flexible bonding wires that can be dynamically routed and tensioned during assembly to achieve optimal connection paths. The bonding wires are attached to external terminals and contact regions in a way that allows for adjustment during manufacturing, enabling the connection length to be minimized while accommodating various terminal positions and assembly requirements.
2Reliability
If the electrical connections are shortened to reduce parasitic effects, then the performance in motor driver applications is improved, but the flexibility in terminal arrangement and ease of manufacture is reduced
Solution Approach 1:
The patent segments the electrical connection path into distinct components: external terminals positioned in space, bonding wires for flexible connection, and contact regions on the chip. This segmentation allows each component to be optimized independently - terminals can be arranged for ease of assembly, bonding wires can be routed to minimize length, and contact regions can be positioned on the chip for optimal electrical performance, thereby resolving the contradiction between simplified arrangement and reduced parasitic effects.
3Length of stationary object
If external terminals are arranged centrally on lateral sides, then the connection length to drain and source contact regions is minimized, but the arrangement complexity for multiple outputs increases
Solution Approach 1:
The patent employs asymmetric arrangement of external terminals relative to the semiconductor chip. The first external terminal is positioned centrally on a first lateral side for optimal connection to the drain contact region, while the second external terminal is positioned centrally on a second lateral side for the source contact region. This asymmetric positioning optimizes connection lengths for each terminal while the systematic pattern maintains manufacturing feasibility.
Data Source
AI summary
A semiconductor package comprises an encapsulation having a first lateral side and an opposite second lateral side, at least one power semiconductor chip having a drain contact region running along the first lateral side, a source contact region running along the second lateral side, and first and second inner contact regions arranged between the drain and source contact regions, a first external terminal which is connected to the drain contact region, is arranged centrally on the first lateral side, and is configured to apply a supply voltage for the at least one power semiconductor chip, a second external terminal which is connected to the source contact region, is arranged centrally on the second lateral side, and is configured to apply a reference voltage for the at least one power semiconductor chip, third and fourth external terminals which are connected to the first inner contact region. are arranged opposite each other at a first end of the first and second lateral sides, respectively, and are configured a first output of the semiconductor package, and fifth and sixth external terminals which are connected to the second inner contact region and are arranged opposite each other at a second end of the first and second lateral sides, respectively, and are configured as a second output of the semiconductor package.