Power Semiconductor Module Parasitic Inductance Control
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Solution Overview
Problem
Power semiconductor modules face challenges in reducing switching time and switching loss, particularly due to variations in parasitic inductance among MOSFETs connected in parallel, which can lead to destruction and reliability issues during switching.
Innovation Solution
Incorporating slits or holes in the metal layers of the power semiconductor module to increase parasitic inductance and reduce variations among MOSFETs, thereby minimizing switching loss and enhancing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If MOSFETs are connected in parallel to increase current capacity, then power handling capability is improved, but parasitic inductance variations increase causing reliability deterioration
Solution Approach 1:
The patent changes the physical structure of metal layers by introducing slits and holes, which modifies the parasitic inductance parameter. This structural parameter change ensures that parasitic inductance values across parallel MOSFETs remain within a controlled ratio (0.9-1.1), thereby maintaining switching reliability while preserving increased current capacity from parallel connection.
Solution Approach 2:
The patent applies different structural modifications to different regions of the metal layers. Slits are positioned closer to source/drain electrodes while holes are positioned closer to gate electrodes, creating localized structural variations that collectively balance the overall parasitic inductance across parallel MOSFETs.
2Loss of energy
If switching time is reduced to decrease switching loss, then power consumption is improved, but reliability deteriorates due to increased parasitic inductance variations
Solution Approach 1:
The patent modifies the electrical parameter of parasitic inductance by changing the physical structure of metal layers. By controlling parasitic inductance values to remain within a narrow ratio range, the patent enables faster switching speeds and reduced switching loss while preventing reliability deterioration that would otherwise result from parasitic inductance variations.
3Ease of manufacture
If metal layer structure is simplified for ease of manufacture, then manufacturing complexity is reduced, but parasitic inductance control capability deteriorates
Solution Approach 1:
The patent segments the metal layers by introducing slits and holes, transforming continuous metal layers into segmented structures. This segmentation approach enables precise control of parasitic inductance while maintaining compatibility with standard semiconductor manufacturing processes, thus achieving both manufacturing feasibility and electrical parameter control.
4Loss of energy
If parasitic inductance is increased to reduce switching current, then switching loss is reduced, but switching time increases reducing productivity
Solution Approach 1:
The patent optimizes the parasitic inductance parameter by controlling it within a specific ratio range rather than simply increasing or decreasing it. This parameter control enables reduced switching loss while maintaining sufficiently fast switching speeds, avoiding the productivity reduction that would result from excessive parasitic inductance.
Data Source
AI summary
According to an embodiment, provided is a semiconductor device includes an insulating substrate; a first main terminal; a second main terminal; an output terminal; a first metal layer connected to the first main terminal; a second metal layer connected to the second main terminal; a third metal layer disposed between the first metal layer and the second metal layer and connected to the output terminal; a first semiconductor chip and a second semiconductor chip provided on the first metal layer; and a third semiconductor chip and a fourth semiconductor chip provided on the third metal layer. The second metal layer includes a first slit. Alternatively, the third metal layer includes a second slit.