Power Semiconductor Module with Isolated Explosion Chambers

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Solution Overview

Problem

Power semiconductor modules in high voltage applications are prone to explosion, causing damage to adjacent modules due to uncontrolled high voltage, leading to structural complexity, increased thickness, and inadequate fastening of bus bars.

Innovation Solution

A power semiconductor module design featuring multiple plates with device receiving portions and bus bar configurations that isolate and secure power semiconductor devices, reduce thickness, and enhance fastening through connecting electrodes, ensuring minimal contact resistance and explosion containment.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If power semiconductor devices are connected in series for high voltage applications, then voltage handling capability is improved, but explosion risk and damage to adjacent modules increases

Engineering Contradiction:
Improvevoltage handling capabilityVSAvoidexplosion damage to adjacent modules
Core Design Contradiction:
PowerVSObject-affected harmful factors

Solution Approach 1:

The module divides power semiconductor devices into separate isolated chambers using partition walls. Each chamber contains individual devices and can contain explosions independently, preventing damage propagation to adjacent devices while maintaining series connection for high voltage handling.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The partition walls act as intermediary structures between adjacent power semiconductor devices. These walls provide physical separation and explosion containment, serving as a barrier that prevents harmful effects from transferring between devices while allowing the module to function as an integrated high voltage system.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If multiple plates and partition walls are added for device isolation, then explosion-proof performance is improved, but structural complexity increases

Engineering Contradiction:
Improveexplosion-proof performanceVSAvoidstructural complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The partition walls serve multiple functions simultaneously: they provide mechanical support for mounting power semiconductor devices, create explosion-containing chambers, provide thermal management pathways, and enable modular assembly. This multi-functionality reduces the need for additional specialized components.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The design merges the functions of device mounting, explosion containment, and thermal management into a single integrated plate and partition wall structure. By combining these functions rather than using separate components, the overall structural complexity is reduced while maintaining explosion-proof performance.

Inventive Principle:
Principle #5Merging (Combining)

3Device complexity

If device receiving portions are formed on inner surfaces of plates, then structure is simplified, but manufacturing precision requirements increase

Engineering Contradiction:
Improvestructural simplicityVSAvoidprecision of device receiving portions
Core Design Contradiction:
Device complexityVSManufacturing precision

Solution Approach 1:

The device receiving portions are pre-formed on the inner surfaces of the plates during plate manufacturing, before assembly. This preliminary action ensures precise positioning and dimensions are built-in during the plate fabrication process, reducing the need for post-assembly adjustments and simplifying the overall assembly process.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10892226B2Power semiconductor module
Publication Date: 2021.01.12 LSIS CO LTD
  • US10892226B2 patent drawing
  • US10892226B2 patent drawing
  • US10892226B2 patent drawing

AI summary

A power semiconductor module may include a first plate, a second plate configured to include first and second device receiving portions thereinside, and coupled to one side of the first plate, first and second power semiconductor devices arranged in the first and second device receiving portions, first and second input bus bars coupled to an outside of the second plate, a third plate configured to include third and fourth device receiving portions thereinside, and coupled to the other side of the first plate, third and fourth power semiconductor devices arranged in the third and fourth device receiving portions, and third and fourth input bus bars coupled to an outside of the third plate.