Power Semiconductor Device Terminal Alignment and Sealing
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Solution Overview
Problem
Power semiconductor elements are prone to damage during the manufacturing process due to over stress on connection sections and gaps between molds when sealing, particularly when the positive and negative electrode terminals are laminated.
Innovation Solution
A power semiconductor device design featuring a polyhedron-shaped first sealing member, aligned positive and negative electrode terminals, and a second sealing member that seals part of the terminals, with the terminals protruding in a layered state to prevent over stress and damage, and a case with heat dissipation fins to manage thermal stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the positive electrode-side terminal and the negative electrode-side terminal are laminated, then the space utilization is improved, but the manufacturing precision deteriorates due to thickness variation causing over stress and gaps during mold clamping
Solution Approach 1:
A resin layer is introduced as an intermediary substance between the positive electrode-side terminal and the negative electrode-side terminal. This resin layer compensates for thickness variations in the laminated structure, ensuring uniform contact during mold clamping and preventing both gaps and excessive stress concentration, thereby resolving the manufacturing precision issue while maintaining the space-saving laminated configuration
Solution Approach 2:
The thickness of the resin layer is specifically controlled to match the thickness difference between the laminated terminals. By adjusting this parameter, the overall thickness of the laminated terminal assembly becomes uniform, enabling precise mold clamping without causing stress concentration or gaps during the sealing process
2Device complexity
If the terminals are laminated in a compact arrangement, then the device complexity is reduced, but the reliability deteriorates due to over stress on connection sections causing power semiconductor element damage
Solution Approach 1:
The resin layer is placed beforehand between the laminated terminals to provide cushioning and stress distribution. This prevents excessive stress from concentrating on the connection sections between the power semiconductor elements and the terminals during the sealing process, thereby protecting the power semiconductor elements from damage while maintaining the compact laminated structure
3Manufacturing precision
If the terminals are clamped tightly during sealing, then the sealing quality is improved, but the strength deteriorates due to over stress damaging the power semiconductor elements
Solution Approach 1:
The resin layer serves as a mediator that enables tight mold clamping for high-quality sealing while simultaneously preventing excessive stress from being transmitted to the power semiconductor elements. The resin deforms to fill gaps and distribute pressure uniformly, achieving both good sealing and protection of the fragile connection sections
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively prevents damage to power semiconductor elements during manufacturing by aligning and sealing the terminals to prevent over stress and enhances heat dissipation, improving the reliability and efficiency of the power conversion process.
Implementation Method 1
a case with heat dissipation fins to manage thermal stress
Data Source
AI summary
A semiconductor module includes a first power semiconductor element having a first surface and a second surface. The semiconductor module also includes a second power semiconductor element having a first surface and a second surface. The semiconductor module also includes first, second, third, and fourth conductor plates, and a connecting part. The connecting part is integrally formed with the second conductor plate, extends toward the third conductor plate, and is connected to the third conductor plate.