Power Semiconductor Device with Trench Gate and Low-Doped Anode
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Solution Overview
Problem
Power semiconductor devices, such as PIN diodes, face challenges in improving reverse recovery characteristics while maintaining high avalanche breakdown voltage and avoiding increased reverse leak current due to defects in the lifetime control region, which also affects the IGBT region's threshold voltage and on-state voltage.
Innovation Solution
A low injection-type PIN diode design is implemented with a p-type anode layer having reduced p-type impurity concentration and trenches with conductive bodies, which reduces carrier concentration and suppresses depletion layer spread towards the anode electrode, enhancing reverse recovery characteristics and breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a lifetime control region with defects is provided in the active layer to reduce carrier concentration and improve reverse recovery characteristics, then reverse recovery characteristics are improved, but reverse leak current increases due to the defects
Solution Approach 1:
The invention changes the physical-chemical parameters of the active layer by reducing carrier concentration through specific doping techniques (such as forming a low-doped region or using doping concentration gradients) rather than introducing defects. This parameter change achieves reverse recovery improvement without the harmful side effect of increased reverse leak current that would result from defect-based lifetime control
Solution Approach 2:
The invention converts the approach from using harmful defects (which shorten carrier lifetime but increase leak current) to using controlled doping parameter changes (which achieve the same lifetime reduction effect without the harmful leak current increase). The harmful effect of defects is avoided while achieving the beneficial reverse recovery characteristic
2Loss of time
If the total impurity amount of the p-type region of the anode layer is reduced to reduce hole injection into the active layer, then reverse recovery characteristics are improved, but avalanche breakdown voltage decreases due to depletion layer spread
Solution Approach 1:
The invention applies local quality by creating a spatially varying doping concentration distribution within the active layer. A low-doped region is formed in specific areas or with specific concentration gradients, which locally controls carrier concentration to improve reverse recovery characteristics while maintaining adequate breakdown voltage in other regions through appropriate doping levels
Solution Approach 2:
The active layer is segmented into regions with different doping concentrations, such as a low-doped region and a normal-doped region, or a doping concentration gradient structure. This segmentation allows different parts of the active layer to serve different functions: the low-doped region improves reverse recovery while the normal-doped regions maintain breakdown voltage
3Device complexity
If the FWD and IGBT are formed in the same chip to downsize the package and reduce costs, then device integration and cost are improved, but the IGBT region is affected by the lifetime control region formation
Solution Approach 1:
The invention applies local quality by making the doping concentration distribution in the active layer position-dependent and device-type-dependent. The FWD region has a low-doped structure to optimize reverse recovery characteristics, while the IGBT region maintains appropriate doping levels to ensure proper threshold voltage and on-state voltage characteristics, allowing both devices to coexist on the same chip without mutual interference
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves improved reverse recovery characteristics and high avalanche breakdown voltage without increasing reverse leak current, while maintaining low on-state voltage and reducing the risk of depletion layer breakdown.
Implementation Method 1
a depleted region is provided in the active layer on the anode electrode side. The depleted region suppresses spread of a depletion layer towards the anode electrode
Implementation Method 2
a low injection-type PIN diode design is implemented with a p-type anode layer having reduced p-type impurity concentration and trenches with conductive bodies, which reduces carrier concentration
Data Source
AI summary
A power semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a pair of conductive bodies, a third semiconductor layer of the second conductivity type, and a fourth semiconductor layer of the first conductivity type. The second semiconductor layer is provided on the first semiconductor layer on the first surface side. The pair of conductive bodies are provided via an insulating film in a pair of first trenches extending across the second semiconductor layer from a surface of the second semiconductor layer to the first semiconductor layer. The third semiconductor layer is selectively formed on the surface of the second semiconductor layer between the pair of conductive bodies and has a higher second conductivity type impurity concentration in a surface of the third semiconductor layer than the second semiconductor layer.