Power Source Circuit with Parallel Boosting Circuits for Ripple Reduction
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Solution Overview
Problem
Conventional power source circuits for semiconductor storage devices like NAND type flash memory experience increased ripple in output potential when set potential is low, leading to deteriorated writing characteristics and erroneous writing due to fixed switching time and varying cell characteristics.
Innovation Solution
A power source circuit with multiple boosting circuits connected in parallel, where the number of active boosting circuits is adjusted based on set potential to control boosting capability, reducing set potential dependency and ripple by varying the voltage dividing ratio and using a logic circuit to manage clock signals for each boosting circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the resistance value of voltage dividing resistors is increased to reduce power consumption, then the RC time constant increases and causes larger ripple in output potential, but decreasing resistance increases power consumption
Solution Approach 1:
The voltage dividing circuit uses switchable resistors that can dynamically change their resistance values based on operating conditions. This allows the circuit to optimize between power consumption and ripple reduction by selecting appropriate resistance combinations, rather than being fixed at a single resistance value.
Solution Approach 2:
The invention changes the resistance parameters of the voltage dividing circuit by providing multiple resistor configurations. Different resistance values can be selected to match different operating modes, allowing the system to adapt to varying requirements for power efficiency and output stability.
2Speed
If the boosting capability of the boosting circuit is increased to improve voltage restoration speed, then the ripple in output potential is increased, but decreasing boosting capability slows down voltage restoration
Solution Approach 1:
The voltage dividing circuit dynamically adjusts its resistance values based on the operating state of the boosting circuit. When the boosting circuit operates at high capability, the voltage dividing circuit selects resistance values that minimize ripple. When boosting capability is reduced, the resistance values are adjusted to allow faster voltage restoration, thus optimizing the trade-off between these two parameters.
Solution Approach 2:
The voltage detecting circuit provides feedback about the output potential state to control the voltage dividing circuit's resistance selection. This feedback mechanism allows the system to automatically adjust the voltage dividing ratio to compensate for ripple conditions, maintaining optimal performance across varying boosting capabilities.
3Loss of time
If the operation delay of the comparison amplifier is reduced to decrease switching time, then power consumption increases, but increasing delay reduces power consumption while maintaining fixed switching time
Solution Approach 1:
The voltage dividing circuit adapts its resistance values based on the switching state of the boosting circuit. During switching transitions, the circuit selects resistance combinations that minimize the RC time constant, thereby reducing switching time. During steady-state operation, it selects higher resistance values to reduce power consumption, thus optimizing performance across different operational phases.
4Productivity
If the set potential is lowered to improve writing speed for cells with low write-enable potential, then the output current increases and ripple is increased, but increasing set potential reduces current and ripple while slowing down writing
Solution Approach 1:
The voltage dividing circuit provides multiple resistance configurations that allow the set potential to be adjusted according to writing requirements. When writing to cells with low write-enable potential, lower set potentials can be selected to improve writing speed. When writing to cells with higher requirements, higher set potentials reduce ripple and current, thus accommodating different writing scenarios.
Solution Approach 2:
The circuit dynamically selects appropriate resistance values in the voltage dividing circuit based on the writing operation requirements. This allows the system to adapt the set potential and corresponding output characteristics to match the specific needs of different memory cells, optimizing both writing speed and output stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the set potential dependency of the output restoration time and ripple, improving writing characteristics by adjusting the number of active boosting circuits and voltage dividing ratios, thereby minimizing erroneous writing and enhancing the stability of the output potential.
Implementation Method 1
a voltage dividing circuit and a comparison amplifier, and an output terminal of the boosting circuit and a ground potential are connected in series via the voltage dividing circuit. The comparison amplifier compares a monitor potential outputted by the voltage dividing circuit with a reference potential.
Implementation Method 2
The comparison amplifier compares a monitor potential outputted by the voltage dividing circuit with a reference potential.
Implementation Method 3
The boosting circuit boosts the power source voltage by being constituted in such a manner that a MOS transistor and a capacitor are connected in series, and one end of the capacitor is connected with mutually complementary CLK and CLKB signals.
Data Source
AI summary
A power source circuit adapted to output a first set potential which is set according to a first selection signal, or a second set potential which is set according to a second selection signal and higher than the first set potential, has an output terminal adapted to output the first set potential or the second set potential; a first boosting circuit adapted to boost a voltage supplied from a power source and to output the boosted voltage to the output terminal; a second boosting circuit adapted to boost the voltage supplied from the power source and to output the boosted voltage to the output terminal; a voltage dividing circuit adapted to output a monitor potential by dividing the output potential outputted from the output terminal according to the first selection signal, or to output a monitor potential by dividing the output potential and reducing a voltage dividing ratio of the monitor potential with respect to the output potential according to the second selection signal; a comparison amplifier adapted to compare the monitor potential with a reference potential, and to output a flag signal for activating the boosting circuit when the monitor potential is lower than the reference potential; and a logic circuit adapted to receive the flag signal from the comparison amplifier, and when receiving the first selection signal, to output a first clock signal for making the first boosting circuit perform the boosting operation, and adapted to receive the flag signal from the comparison amplifier, and when receiving the second selection signal, to output a second clock signal for making the second boosting circuit perform the boosting operation, together with the first clock signal.