Multi-Core Power State Controller for Voltage Undershoot Mitigation
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Solution Overview
Problem
Multi-core data processors face power supply voltage fluctuations due to sudden changes in circuit activity, leading to potential malfunctions and the need for conservative design practices with large guardbands, which can result in slower operation and failed functional tests.
Innovation Solution
Implementing a power state controller in each data processor core that allows staged or slower transitions from idle to active states based on elapsed time and core identification, reducing the reliance on external circuits for coordinated power state changes and minimizing guardband requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a large guardband is added to extend the voltage range, then the circuit reliability is improved, but the operating speed deteriorates and functional tests fail
Solution Approach 1:
The patent applies preliminary action by having data processor cores enter an idle state before encountering a barrier, rather than remaining active. This pre-transition to idle state reduces circuit activity and prevents power supply voltage undershoot before it occurs, thereby maintaining reliability without requiring a large guardband that would slow down operation.
Solution Approach 2:
The patent implements dynamics by dynamically adjusting the power state of data processor cores based on runtime conditions. Cores transition between active and idle states depending on whether they are waiting at a barrier or not, allowing the system to adapt its power consumption and voltage requirements in real-time, thus maintaining reliability while preserving operating speed.
2Productivity
If data processor cores are released simultaneously from idle state, then the productivity is improved, but the power supply voltage undershoot worsens
Solution Approach 1:
The patent applies segmentation by dividing the simultaneous release of multiple data processor cores into staged transitions. Instead of all cores transitioning from idle to active state at the same time, they do so in sequences or at different rates, which segments the spike in circuit activity and prevents severe power supply voltage undershoot while still maintaining high productivity.
Solution Approach 2:
The patent implements periodic action by introducing controlled delays or staggered timing in the release of data processor cores from idle state. This periodic or sequential activation pattern spreads out the power consumption demand over time, reducing the peak undershoot effect while preserving overall system productivity.
Data Source
AI summary
A multi-core data processor includes multiple data processor cores and a circuit. The multiple data processor cores each include a power state controller having a first input for receiving an idle signal, a second input for receiving a release signal, a third input for receiving a control signal, and an output for providing a current power state. In response to the idle signal, the power state controller causes a corresponding data processor core to enter an idle state. In response to the release signal, the power state controller changes the current power state from the idle state to an active state in dependence on the control signal. The circuit is coupled to each of the multiple data processor cores for providing the control signal in response to current power states in the multiple data processor cores.