Multi-Path Power Switch Wakeup to Limit IC Power Supply Noise
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Solution Overview
Problem
Integrated circuits face challenges in power management due to leakage currents in idle transistors, leading to static power consumption and noise on power supply connections, which can cause erroneous operation and increase delay in power gated block enablement, especially with variations in semiconductor fabrication, voltage, and temperature.
Innovation Solution
A multi-path power switch scheme is introduced, where first and second groups of power switches are activated sequentially, with a timer controlling the interval between activations to manage current flow and reduce power supply noise, allowing for controlled power-up of functional blocks to prevent excessive current and di/dt during power-on procedures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If power switches are activated simultaneously to enable a power gated block, then the power-up time is reduced, but power supply noise and transient currents increase due to rapid current flow changes
Solution Approach 1:
The power switch activation is divided into multiple groups that are activated sequentially rather than simultaneously. The power gated block is segmented into regions corresponding to different switch groups, with each group activated in a controlled sequence to limit di/dt while ultimately achieving full power-up
Solution Approach 2:
The power switch activation sequence is pre-determined and controlled based on expected fast process-voltage-temperature (PVT) conditions. The controller pre-schedules which switches activate at what times, ensuring that even under fast conditions where simultaneous activation would cause harmful noise, the sequential activation pattern is maintained
2Object-affected harmful factors
If power switches are activated sequentially to reduce power supply noise, then power supply noise is reduced, but the power-up time increases
Solution Approach 1:
The activation sequence is dynamically adapted based on monitored current flow characteristics. The controller observes actual di/dt behavior and adjusts the timing and grouping of subsequent switch activations accordingly, optimizing the balance between noise reduction and power-up speed rather than using a fixed sequential pattern
3Productivity
If more power switches are activated at the same time, then the power-up speed increases, but the rate of current change (di/dt) exceeds maximum limits causing erroneous operation
Solution Approach 1:
The system continuously monitors current flow and di/dt parameters during power-up and uses this feedback to control the activation sequence. When di/dt approaches maximum limits, the controller delays or redistributes switch activations to maintain safe operating levels, preventing erroneous operation while still achieving efficient power-up
Data Source
AI summary
A multi-path power switch scheme for functional block wakeup is disclosed. The scheme may be applied to functional blocks of an integrated circuit. When a power on procedure is initiated within a given functional block, a first group of power switches in a functional block may be powered on, while a second group of power switches is inhibited from powering on. After a predetermined time has elapsed, activation of the second group of power switches is initiated. After initiation of a power up procedure for a given functional block, the powering up of a second functional block to be powered on may initially be inhibited. After a predetermined time has elapsed, the powering on of the second functional block may be initiated. Overlap between times when the first and second groups of switches are active may depend on process, voltage, and temperature variations.