Multi-Stage Power Switching Circuit for Surge Current Reduction
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Solution Overview
Problem
Conventional power switching in integrated circuits leads to significant surge currents during power-up, causing power supply buckling, metal interconnect electromigration, and noise introduction into neighboring blocks due to large instantaneous current spikes.
Innovation Solution
A system and method utilizing a power switching circuit with two sets of transistors, where a first set pre-charges the power rail to a voltage less than the supply voltage and a second set ramps it to the full supply voltage, reducing surge currents through a controlled power-up sequence.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a head switch or foot switch is activated to reduce leakage currents, then power consumption is reduced, but large instantaneous current spikes are introduced during activation and deactivation
Solution Approach 1:
The power switching circuit is divided into multiple transistor stages (first set of transistors Q1-Q4 and second set of transistors Q5-Q8) that operate sequentially. The first set of transistors activates initially to begin charging the power grid, then the second set activates to complete the charging process. This segmentation of the switching function into multiple stages prevents any single switch from having to handle the entire charging current, thereby reducing instantaneous current spikes while maintaining effective leakage current control.
2Power
If a single switch is used to charge the power grid from ground voltage to supply voltage, then the power grid is fully charged, but a large instantaneous current is introduced due to the large capacitance
Solution Approach 1:
The first set of transistors (Q1-Q4) acts as preliminary switching elements that activate first to begin charging the power grid to an intermediate voltage level. Only after these transistors are activated does the second set of transistors (Q5-Q8) activate to complete the charging process to the full supply voltage. This preliminary action approach allows the power grid capacitance to charge gradually in stages rather than all at once, significantly reducing the instantaneous current spike that would occur with single-switch rail-to-rail charging.
3Loss of time
If rapid charging of the power grid is performed, then power-up time is reduced, but power supply buckling and metal interconnect electromigration occur due to large current spikes
Solution Approach 1:
The power-up process is structured as a periodic or sequential multi-stage operation where the first set of transistors activates initially, charges the power grid partially, then the second set of transistors activates to complete the charging. This periodic activation pattern distributes the charging current over time rather than delivering it all at once, maintaining reliability by preventing power supply buckling and electromigration while still achieving relatively fast power-up through the coordinated action of both transistor sets.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes surge currents, protects low power circuitry from power-up related damage, reduces noise, and enhances power supply noise immunity between adjacent devices.
Implementation Method 1
a power grid of a circuit device may represent a large capacitance (C). When a head switch or foot switch is activated to enable charging of the power grid, a large instantaneous current (ipower—up) may be introduced.
Implementation Method 2
the rail-to-rail charging of the power grid from a voltage level at or near an electrical ground voltage level to a voltage level (VDDx) that is approximately equal to a supply voltage level (e.g., VDD) can introduce a significant current
Data Source
AI summary
In a particular illustrative embodiment, a system is disclosed that includes a first power domain that is responsive to a first power switching circuit and a second power domain that is responsive to a second power switching circuit. The system also includes a logic circuit adapted to selectively activate the first power switching circuit and the second power switching circuit. At least one of the first power switching circuit and the second power switching circuit includes a first set of transistors adapted for activation during a first power up stage and a second set of transistors adapted for activation during a second power up stage after at least one of the first set of transistors are activated.