Power Transistor Wafer Testing with Sense Transistor Preconditioning
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Solution Overview
Problem
Wafer testing of power transistors is difficult due to the inability of fine probe needles to carry significant amounts of power, making it challenging to measure current properties effectively.
Innovation Solution
Utilize a sense transistor constructed using the same epitaxial stack as the power transistor, pre-condition it by alternately turning it on and off multiple cycles while allowing the power transistor's source terminal to float, and simulate operating conditions by heating the wafer to match expected temperatures, allowing for accurate current property measurement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If fine probe needles are used for wafer testing, then measurement precision is improved, but power carrying capability deteriorates
Solution Approach 1:
The patent introduces a sense transistor as an intermediary device between the fine probe needles and the power transistor. The sense transistor has a drain terminal connected to the power transistor's drain terminal, allowing it to sense the current flowing through the power transistor without requiring the probe needles to carry high current directly. This mediator enables indirect measurement of high current properties using low-current-capable probes.
Solution Approach 2:
The sense transistor is constructed using the same epitaxial stack as the power transistor, creating a scaled-down copy that replicates the electrical characteristics. By measuring current properties in the sense transistor and scaling the results based on known area ratios, the patent obtains accurate measurements of the power transistor's current properties without subjecting the fine probes to high power loads.
2Productivity
If wafer testing is performed before dicing, then productivity is improved, but testing capability for high current properties deteriorates
Solution Approach 1:
The sense transistor serves as a mediator that enables reliable high-current property measurement during wafer testing. It allows the testing system to accurately assess power transistor performance at the wafer level before dicing, maintaining both productivity and reliability by decoupling the measurement function from the high-current path.
Solution Approach 2:
The sense transistor is constructed and integrated into the wafer during the fabrication process, before dicing occurs. This preliminary preparation enables subsequent wafer-level testing to proceed efficiently with reliable measurements, as the sensing capability is already in place and does not require post-dicing individual device handling.
3Ease of operation
If fine probe needles are used, then ease of operation is improved, but power transmission capability deteriorates
Solution Approach 1:
The sense transistor acts as an intermediary that transfers the current sensing function from the probe needles to the transistor structure itself. The fine probe needles only need to apply small sensing currents to the sense transistor, maintaining ease of operation, while the sense transistor indirectly measures the high current flowing through the power transistor through their shared drain connection.
Data Source
AI summary
Wafer testing of a power transistor for a current property of the power transistor. Wafer testing of a power transistor is performed by using a sense transistor constructed using the same epitaxial stack as was used to construct the power transistor. The current property of the sense transistor is then measured, and the current property of the power transistor can be determined from that measurement. Furthermore, the sense transistor is pre-conditioned prior to the measurement by alternately turning on and off the sense transistor multiple cycles while allowing a source terminal of the power transistor to float. This simulates operating conditions of the power transistor, thereby allowing for measurement of the current property of the power transistor as it would likely be in operation.