Power TSVs for Stable Stacked Semiconductor Power Distribution
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Solution Overview
Problem
In stacked semiconductor devices, the intensity of the power source decreases with each incrementally added chip due to increased resistance in the power supply path, leading to unstable power distribution across multiple stacked semiconductor chips.
Innovation Solution
Incorporating power through silicon vias (TSVs) within the active region of each chip, positioned between dummy and reservoir capacitor regions, which are electrically coupled using selected dummy and power lines to provide a direct and stable power supply, reducing resistance and enhancing power delivery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple semiconductor chips are stacked vertically to increase memory capacity, then the memory capacity is improved, but the power source intensity decreases due to increased resistance in the power supply path
Solution Approach 1:
The patent transitions from planar power distribution to three-dimensional power distribution by forming power through-silicon vias (TSVs) that extend vertically through the substrate. This allows power to be delivered from the pad region directly to the active region across multiple stacked chips, reducing the resistance in the power supply path and maintaining power source intensity despite increased memory capacity through vertical stacking.
Solution Approach 2:
The power distribution network is segmented into multiple independent power TSVs that are distributed across the substrate. Instead of relying on a single power path, multiple power TSVs are formed at different locations, each providing an independent power delivery channel. This segmentation reduces the overall resistance and improves power distribution reliability across the stacked chip structure.
2Measurement precision
If power lines are spaced apart to reduce interference, then signal integrity is improved, but the power distribution efficiency decreases due to increased resistance
Solution Approach 1:
The patent moves power delivery from a two-dimensional planar configuration to a three-dimensional structure by forming vertical power TSVs. This allows power lines to remain spaced apart horizontally for signal integrity while the vertical TSVs provide direct power pathways, eliminating the need for long horizontal power traces and reducing resistive losses.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration ensures a stable and consistent power supply to each chip in a stacked semiconductor device by reducing resistance and providing a more direct path for power distribution, maintaining power integrity across multiple layers.
Implementation Method 1
power through silicon vias (TSVs) formed in the active region... A pair of the power TSVs which received a same voltage are electrically coupled
Data Source
AI summary
A semiconductor device including power TSVs for stably supplying a power source is described. A semiconductor device includes a chip power pad placed in a first region of a chip, power through silicon vias (TSVs) connected to the chip power pad and placed in the second region of each of the chips, and metal lines configured to couple the chip power pad and the power TSVs.