Reset Detection Circuit for Missed Reset Assertion at Power-Up
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Solution Overview
Problem
Digital electronic circuits face attacks where the reset signal is prevented from being asserted, leading to unintended features being enabled due to flip flops powering up in an undetermined state, resulting in a 50% chance of incorrect initialization.
Innovation Solution
A dedicated reset detection circuitry system that monitors the assertion of the reset signal and outputs a confirmatory signal, which can trigger a reset signal if not asserted, using a group of flip flops configured to output a predetermined pattern when reset is asserted, and a comparator to verify this pattern, ensuring correct initialization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the reset pin is left unasserted during power-up, then the circuit avoids forced initialization and maintains feature access flexibility, but flip flops enter an undetermined state with 50% probability of incorrect initialization enabling unauthorized features
Solution Approach 1:
The patent implements a feedback mechanism where the reset detection circuit continuously monitors the reset signal state and compares the actual flip-flop output pattern against the expected predetermined pattern. When a mismatch is detected (indicating reset failure), the system generates a correction signal to force proper initialization, thereby maintaining reliability while preserving the adaptability benefit of optional reset assertion.
Solution Approach 2:
The patent applies preliminary action by pre-configuring the flip-flops to produce a specific predetermined pattern when properly reset, and by designing the detection circuit to anticipate this pattern. This preliminary configuration enables the system to detect reset failures and correct them before they can cause unauthorized feature enabling, thus ensuring reliable initialization without forcing reset assertion.
2Reliability
If reset detection circuitry is added to monitor and correct reset failures, then system reliability and initialization correctness are improved, but device complexity increases due to additional circuit components
Solution Approach 1:
The patent merges the reset detection functionality with the existing flip-flop structure by using the flip-flops themselves to generate the predetermined pattern that serves as the detection reference. The detection logic is integrated into the same circuit block that performs the primary function, rather than adding completely separate monitoring circuitry. This merging approach improves reliability while minimizing the increase in device complexity.
Solution Approach 2:
The reset detection circuit serves itself by using its own output pattern as the reference for detection. The flip-flops configured to produce the predetermined pattern simultaneously perform the primary circuit function and provide the reference signal for reset verification. This self-service approach eliminates the need for external reference signals or additional complex comparison logic, thereby improving reliability with minimal complexity overhead.
Data Source
AI summary
There is disclosed a system for detecting the assertion of a reset signal. A plurality of circuit elements is configurable by a reset signal to output a string of data values in a predetermined pattern. A comparator receives the string of data values and determines whether the string of data values matches the predetermined pattern. If so, the comparator generates an output signal indicative of a reset. In one embodiment, the output signal of the comparator can be used to automatically trigger a reset if the reset signal has not been asserted.