Post-Passivation Interconnect Opening Alignment for Thermal Stress Shielding

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Solution Overview

Problem

The coefficient of thermal expansion mismatch between various materials in semiconductor die packaging leads to stress and potential delamination issues when subjected to elevated temperatures, affecting the reliability and yield of semiconductor devices.

Innovation Solution

The implementation of a post-passivation interconnect (PPI) with strategically aligned openings and undercontact metallization (UCM) that shields underlying layers from thermal stresses by positioning extra material from the third passivation layer along the direction of thermal expansion mismatch, reducing the likelihood of delamination and enhancing manufacturing yield.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional solder bump packaging is used with multiple material layers, then electrical connection between semiconductor die and external devices is achieved, but coefficient of thermal expansion mismatch causes stress and delamination at elevated temperatures

Engineering Contradiction:

Improveconnection reliabilityVSAvoidthermal stress

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent introduces an intermediary structure (the opening configuration and additional material layer) between the undercontact metallization and the passivation layers. This intermediary acts as a stress-absorbing element that accommodates thermal expansion differences, preventing direct stress transmission that would cause delamination.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent applies beforehand cushioning by pre-positioning an opening and additional material layer in the stress pathway before thermal cycling occurs. This pre-configured structure serves as a cushion that absorbs and distributes thermal stresses before they can propagate to cause delamination, effectively protecting the bonding interfaces in advance.

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

2Device complexity

If multiple material layers with different coefficients of thermal expansion are stacked, then functional semiconductor die structure is created, but thermal expansion mismatch leads to stress concentration and potential failure

Engineering Contradiction:

Improvemulti-layer structureVSAvoidbonding strength

Core Design Contradiction:

Device complexityVSStrength

Solution Approach 1:

The patent applies local quality by modifying specific localized regions (creating openings and adding material layers at particular positions) rather than changing the entire multi-layer structure. This localized modification strategically addresses stress concentration points while preserving the overall complexity and functionality of the multi-layer device structure.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent segments the continuous material layers by introducing openings, effectively dividing the stress transmission pathway into discrete sections. This segmentation interrupts the propagation of thermal stresses across the entire structure, allowing each segment to accommodate expansion independently and preventing cumulative stress buildup that would weaken bonding.

Inventive Principle:

Principle #1Segmentation

3Ease of manufacture

If standard passivation layers are applied without strategic opening alignment, then semiconductor die is protected, but thermal stresses cause delamination at layer interfaces

Engineering Contradiction:

Improvepassivation processVSAvoidlayer adhesion

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The patent introduces asymmetry by aligning openings perpendicular to the direction of maximum thermal expansion mismatch rather than using symmetric or random patterns. This asymmetric configuration optimizes the stress distribution pathway, creating a more effective barrier against delamination while maintaining manufacturability through standardized alignment procedures.

Inventive Principle:

Principle #4Asymmetry

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution effectively shields underlying layers from thermal expansion mismatches, reducing the risk of delamination and improving the overall yield and reliability of semiconductor devices by aligning PPI openings perpendicular to the direction of thermal expansion mismatch and utilizing extra material from the third passivation layer.

Implementation Method 1

Each one of these different materials may have a unique coefficient of thermal expansion that is different from the other materials. This type of coefficient of thermal expansion mismatch can cause problems if the semiconductor die is subjected to elevated temperatures.

Methodology Applied

Scientific EffectThermal expansion: Thermal Expansion

Data Source

PatentUS9548281B2Electrical connection for chip scale packaging

Publication Date: 2017.01.17 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A system and method for providing a post-passivation opening and undercontact metallization is provided. An embodiment comprises an opening through the post-passivation which has a first dimension longer than a second dimension, wherein the first dimension is aligned perpendicular to a chip's direction of coefficient of thermal expansion mismatch. By shaping and aligning the opening through the post-passivation layer in this fashion, the post-passivation layer helps to shield the underlying layers from stresses generated from mismatches of the materials' coefficient of thermal expansion.