Post-Passivation Interconnect Slots for Adhesion
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Wafer level chip scale packaging (WLCSP) processes face polymer film peeling issues, leading to weak interfaces in post-passivation interconnect (PPI) structures and device failures due to weak interfaces and potential failures in the PPI structure.
Innovation Solution
The method involves forming slots in the passivation layer to enhance adhesion between the passivation layer and subsequent deposited material layers, followed by the formation of a PPI structure with a barrier layer and solder bump, which improves the strength of the PPI structure and reduces peeling and cracking of the polymer layer, thereby increasing joint reliability and reducing bump fatigue.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If polymer films are formed over passivation layers in conventional WLCSP processes, then the PPI structure can be formed, but polymer film peeling occurs leading to weak interfaces and device failures
Solution Approach 1:
The patent applies preliminary action by forming slots in the passivation layer before depositing the polymer film. This pre-prepared structure creates anchoring points that prevent peeling during subsequent processing, resolving the interface strength issue without compromising PPI structure integrity
Solution Approach 2:
The slots created in the passivation layer function as porous structures that allow the polymer film to penetrate and anchor into the passivation layer. This porous configuration significantly enhances adhesion between the polymer film and passivation layer, preventing peeling and strengthening the overall PPI structure
2Ease of manufacture
If conventional PPI formation processes are used, then the basic structure can be created, but peeling and cracking of the polymer layer occur reducing joint reliability
Solution Approach 1:
The slots are formed in advance during the passivation layer processing stage, before polymer deposition. This preliminary action integrates seamlessly into the existing manufacturing flow without adding complex steps, while dramatically improving joint reliability by preventing peeling and cracking
Solution Approach 2:
Rather than modifying the entire passivation layer or polymer film uniformly, the invention applies local quality enhancement by creating slots only in specific regions where adhesion is critical. This localized modification maintains manufacturing simplicity while targeting the specific reliability issues
3Strength
If standard passivation layer structures are used, then the basic protection is provided, but adhesion to subsequent material layers is insufficient causing interface weakness
Solution Approach 1:
The passivation layer is transformed from a solid, non-porous structure to one with controlled porosity through the formation of slots. These porous features dramatically increase adhesion to subsequent material layers without requiring complex multi-layer passivation structures, maintaining relative simplicity while enhancing strength
Solution Approach 2:
The passivation layer is segmented by creating slots that divide the continuous layer into sections. This segmentation increases the surface area and creates mechanical interlocking points for subsequent layers, improving adhesion strength without significantly increasing overall device complexity
Data Source
AI summary
A method of making a semiconductor device includes forming a passivation layer overlying a semiconductor substrate, the semiconductor substrate having a first region and a second region, wherein the first region is a conductive pad and the second region is adjacent to the first region. The method further includes forming a first protective layer overlying the passivation layer and forming an interconnect layer overlying the first protective layer. The method further includes forming a plurality of slots in the second region and forming a second protective layer overlying the interconnect layer, wherein the second protective layer fills each slot of the plurality of slots. The method further includes exposing a portion of the interconnect layer through the second protective layer; forming a barrier layer on the exposed portion of the interconnect layer; and forming a solder bump on the barrier layer.


