P+ Etch Stop Layer for Low-Voltage Vertical Power Devices
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Solution Overview
Problem
Vertical power devices, such as IGTO devices, face significant voltage drops due to thick p+ substrate layers, leading to variability in device characteristics from lot-to-lot, which affects their performance as high-voltage, high-current switches.
Innovation Solution
A thin, low resistivity p+ type etch stop layer is formed using epitaxial growth or implantation, serving as both a carrier injection layer and an etch stop, allowing for precise control of thickness and repeatable fabrication, reducing voltage drops and improving device consistency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thick p+ substrate layer is used, then the device can support high voltage and high current, but the voltage drop across the device increases and device characteristics vary from lot-to-lot
Solution Approach 1:
The substrate structure is segmented into multiple functional layers: a thin p+ etch stop layer (5-20 micrometers) for carrier injection, and a thicker lightly-doped n- drift layer for voltage blocking. This segmentation allows the thin p+ layer to minimize voltage drop while the n- layer maintains high voltage capability, resolving the contradiction between low voltage drop and high voltage support.
Solution Approach 2:
The dopant concentration in the p+ etch stop layer is optimized to be highly doped (10^19 to 10^21 atoms/cm³), creating a low resistivity region that efficiently injects carriers into the drift layer. This parameter optimization reduces the voltage drop across the substrate while maintaining the ability to support high currents, directly addressing the energy loss issue.
2Reliability
If a thick p+ substrate layer is used, then the device can support high current, but the voltage drop increases and manufacturing precision decreases
Solution Approach 1:
The substrate is divided into a thin p+ etch stop layer and a separate n- drift layer. The thin p+ layer (5-20 micrometers) can be precisely controlled during epitaxial growth or ion implantation, eliminating the lot-to-lot variability associated with thick substrate grinding while maintaining structural integrity and current support capability.
Solution Approach 2:
The mechanical substrate thinning process (grinding and polishing) is replaced with epitaxial growth or ion implantation methods to form the thin p+ etch stop layer. These alternative methods provide superior thickness control and repeatability compared to mechanical processes, directly improving manufacturing precision and device characteristics consistency.
3Loss of energy
If a thin p+ etch stop layer is used, then voltage drop is reduced, but the layer must serve dual functions as carrier injection layer and etch stop
Solution Approach 1:
The thin p+ etch stop layer is designed to perform multiple functions simultaneously: (1) serve as an etch stop layer to prevent over-etching during fabrication, (2) act as a carrier injection layer to supply holes to the drift layer for conduction, and (3) provide a low resistivity path to minimize voltage drop. This multi-functionality reduces the need for additional separate layers, simplifying the overall device structure despite the increased functional requirements of the single layer.
Solution Approach 2:
The dopant concentration in the p+ etch stop layer is optimized to be highly doped (10^19 to 10^21 atoms/cm³), which simultaneously enables efficient carrier injection (low resistivity) and provides sufficient etch resistance during fabrication. This parameter optimization allows the thin layer to fulfill multiple functions without requiring increased thickness, maintaining low voltage drop while achieving the necessary structural and functional properties.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The thin, low resistivity p+ etch stop layer significantly reduces voltage drops across the device, enhancing repeatability and performance as a high-voltage, high-current switch with minimal lot-to-lot variability.
Implementation Method 1
a thin, low resistivity p+ type bottom semiconductor layer, having a metal electrode formed on it, for carrier injection
Implementation Method 2
A thin, low resistivity p+ type etch stop layer is formed using epitaxial growth or implantation
Data Source
AI summary
A sacrificial substrate wafer is provided. A low resistivity etch stop layer is formed on or in the top surface of the wafer. The etch stop layer may be a highly doped, p+ type epitaxially grown layer, or an implanted p+ type boron layer, or an epitaxially grown p+ type SiGe layer. Various epitaxial layers, such as an n− type drift layer, and doped regions are then formed over the etch stop layer to form a vertical power device. The starting wafer is then removed by a combination of mechanical grinding/polishing to leave a thinner layer of the starting wafer. A chemical or plasma etch is then used to remove the remainder of the starting wafer, using the etch stop layer to automatically stop the etching. A bottom metal electrode is then formed on the etch stop layer. The etch stop layer injects hole carriers into the drift layer.