PRAM Phase-Change Layer Bismuth Doping for Fast Crystallization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional phase-change random access memories (PRAMs) face challenges with high crystallization temperatures and slow crystallization speeds, leading to difficulties in achieving high operational speeds due to the need for high reset currents and long set times.
Innovation Solution
A PRAM with a phase-change layer made of materials like Ge2(Sb1-xBix)2Te5 or Ge3Bi2Te6, which have lower crystallization temperatures (between 100° C and 150° C) and faster crystallization times (between 1 ns and 50 ns), allowing for reduced programming currents and improved data storage efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If conventional GST phase-change material is used in PRAM, then data storage capability is achieved, but crystallization temperature is high and crystallization speed is slow
Solution Approach 1:
The patent modifies the chemical composition parameters of the phase-change material by incorporating Bismuth (Bi) into the Ge-Sb-Te system, creating Ge2(Sb1-xBix)2Te5 or Ge3Bi2Te6 compositions. This compositional parameter change results in a lower crystallization temperature range (100-150°C) and faster crystallization speed (1-50 ns) compared to conventional GST materials
Solution Approach 2:
The patent creates a composite phase-change material system by combining multiple elements (Ge, Sb, Te, and Bi) in specific ratios. The Ge2(Sb1-xBix)2Te5 and Ge3Bi2Te6 compositions represent composite materials where Bismuth acts as a dopant that modifies the crystallization properties of the base GST material, achieving both lower temperature and faster speed
2Use of energy by moving object
If conventional GST phase-change material is used in PRAM, then data storage is enabled, but reset current requirement is high
Solution Approach 1:
The patent changes the electrical and thermal parameters of the phase-change material through compositional modification. The Ge2(Sb1-xBix)2Te5 and Ge3Bi2Te6 materials exhibit modified electrical conductivity and thermal properties that enable achieving the necessary resistance state changes (amorphous to crystalline) with lower current pulses, reducing the programming current requirement while maintaining data storage reliability
3Loss of time
If conventional GST phase-change material is used in PRAM, then memory function is achieved, but set time is long
Solution Approach 1:
The patent achieves faster set time (crystallization time) by modifying the material's kinetic parameters through compositional changes. The Ge2(Sb1-xBix)2Te5 and Ge3Bi2Te6 materials exhibit enhanced atomic mobility and faster phase transition kinetics, enabling crystallization to complete within 1-50 nanoseconds, which directly improves operational speed and reduces the time penalty for data writing operations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables faster data storage and reduced programming currents, enhancing the operational speed and data integrity of PRAMs by utilizing materials with lower crystallization temperatures and shorter crystallization times.
Implementation Method 1
a phase-change layer formed of a material having a lower crystallization temperature and quicker information storing time because of a faster crystallization speed than a conventional GST phase-change material
Implementation Method 2
when an electrical pulse is applied to the phase-change material, a state of the phase-change material changes between crystalline and amorphous states according to heat generated in a localized area
Implementation Method 3
heat generated in a localized area
Data Source
AI summary
A memory system includes a memory cell array having a plurality of memory sectors. Each memory sector includes a plurality of memory cells. The memory system further includes a controller configured to write data to the memory cell array in response to a writing signal. The controller is further configured to refresh a memory sector among the plurality of memory sectors each time a writing signal is provided. When N (N is a positive integer) memory cells are programmed, a programming current is less than or equal to about 0.75 mA*N.