Power Supply Circuit for Phase-Change Random Access Memory Voltage Stability
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Solution Overview
Problem
Phase-change Random Access Memory (PRAM) experiences write and read malfunctions due to voltage level changes, which existing technologies fail to adequately address.
Innovation Solution
A power supplying circuit (PSC) is designed for PRAM, featuring a first voltage generator for read/standby voltage and a second voltage generator with a voltage pump unit, pump output detector, discharging unit, and control unit to manage and discharge voltages effectively, ensuring stable voltage levels across memory blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If voltage level changes occur in PRAM, then write and read operations can be performed, but malfunctions occur due to voltage instability
Solution Approach 1:
The power supplying circuit performs preliminary voltage stabilization before write and read operations. The circuit pre-charges or pre-discharges voltage lines to target levels, ensuring voltage stability is established before memory operations begin, thereby preventing malfunctions caused by voltage fluctuations during operations.
Solution Approach 2:
The power supplying circuit monitors voltage levels on memory block lines and dynamically adjusts voltage supply based on detected voltage conditions. This feedback mechanism detects voltage deviations and corrects them in real-time, maintaining stable voltage levels throughout write and read operations to prevent malfunctions.
2Productivity
If voltage is supplied to memory blocks, then memory operations can proceed, but voltage rising/falling time increases operation delay
Solution Approach 1:
The power supplying circuit pre-charges voltage lines to intermediate levels before actual memory operations. By preparing voltage lines in advance to near-target levels, the circuit reduces the time required for voltage transitions during actual operations, thereby decreasing operation delay while maintaining high productivity.
Solution Approach 2:
The power supplying circuit uses periodic pulsing to charge or discharge voltage lines in controlled stages. Instead of single large voltage transitions, the circuit applies multiple smaller voltage steps over time, reducing electromagnetic interference and allowing faster overall voltage establishment while maintaining operation speed.
3Reliability
If voltage is maintained stable across memory blocks, then malfunctions are prevented, but power consumption increases
Solution Approach 1:
The power supplying circuit applies voltage stabilization only to specific memory blocks or line segments that require it, rather than uniformly stabilizing all voltage lines throughout the memory array. This localized approach maintains operation stability in critical areas while minimizing power consumption in areas where full stabilization is unnecessary.
Solution Approach 2:
The power supplying circuit applies voltage stabilization selectively during specific operation phases rather than continuously. By stabilizing voltage only when needed for particular write or read operations and allowing voltage to float during idle periods, the circuit maintains reliability during operations while significantly reducing overall power consumption.
Data Source
AI summary
A power supplying circuit (PSC) and a phase-change random access memory (PRAM) including the PSC. According to an aspect of the invention, the PSC includes: a first voltage generator configured to output a first voltage to a first terminal; and a second voltage generator configured to output a second voltage to a second terminal, the second voltage generator including: a voltage pump unit configured to output the second voltage based on a clock signal and a pump control signal; a pump output detector coupled to the voltage pump unit, the pump output detector configured to output a pump output detection signal; and a discharging unit coupled to the voltage pump unit, the discharging unit configured to discharge a level of the second voltage to a predetermined level in response to a discharge signal. Embodiments of the invention may prevent write and/or read malfunctions that can occur due to changes in the level of a voltage supplied to PRAM cell blocks.