Self-Aligned Contacts for Programmable Resistive RAM
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Solution Overview
Problem
The challenge in manufacturing small electrical contacts for programmable resistive RAM cells in integrated circuits is the reliance on aggressive photolithography masks, which complicates the alignment with existing layers and increases the risk of errors.
Innovation Solution
A self-aligned method is developed to form interlayer contacts with a step profile, using dielectric layers with etching selectivity differences to reduce the cross-section of the contacts to less than 60 nm, allowing for the formation of small electrical contacts without relying on traditional photolithographic masks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional photolithographic masks are used to define small electrical contacts, then the alignment with existing layers becomes complex and error-prone, but the contacts can still be formed with sufficient size
Solution Approach 1:
The patent implements self-aligned contact formation where the contact holes are automatically positioned using the underlying transistor gate structure as a reference. The gate pattern serves as a self-aligning mask that defines the contact location without requiring separate photolithographic alignment steps, thereby achieving precise contact positioning while eliminating mask alignment complexity
Solution Approach 2:
The gate structure is formed first as a preliminary step that simultaneously serves multiple functions: it defines the transistor active area and pre-establishes the reference pattern for subsequent contact hole alignment. This preliminary gate formation enables the contacts to be automatically positioned at the correct location without additional alignment operations
2Area of moving object
If the contact cross-section is reduced to increase density, then the manufacturing precision requirements increase, but the device area is reduced
Solution Approach 1:
The patent employs parameter changes in the etching process, using selective etching conditions that exploit the self-aligned geometry to achieve precise contact dimensions. By controlling etch selectivity and using the gate structure as a physical stop, the method achieves accurate contact size control at reduced dimensions without proportionally increasing manufacturing difficulty
Solution Approach 2:
The contact holes are formed nested within the gate structure footprint, with the contact dimensions being a subset of the gate dimensions. This nesting relationship automatically ensures proper sizing and positioning, as the contact holes are confined by the gate pattern boundaries, thereby controlling contact dimensions while maintaining area reduction
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the precise formation of small electrical contacts, improving the manufacturing process by reducing the complexity of mask alignment and enhancing the reliability of programmable resistive RAM cells in integrated circuits.
Implementation Method 1
using dielectric layers with etching selectivity differences to reduce the cross-section of the contacts to less than 60 nm
Data Source
AI summary
Programmable resistive RAM cells have a resistance that depends on the size of the contacts. Manufacturing methods and integrated circuits for lowered contact resistance are disclosed that have contacts of reduced size.