Pre-routing Repeater Insertion for Chip Net Segmentation
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Solution Overview
Problem
Chip-level routing is time-consuming and labor-intensive due to the need for custom route attention in high-performance chips, where designers must manually control net topologies and insert repeaters, often requiring re-routing when chip floor plans are modified.
Innovation Solution
Assigning and inserting repeaters into nets prior to physical routing, dividing long nets into subnets, and performing routing by connecting these subnets, which simplifies the routing process and reduces the need for complex interactive router features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If custom route attention is applied to high-performance chips, then routing quality and timing performance are improved, but routing time and process complexity increase significantly
Solution Approach 1:
The patent applies preliminary action by inserting repeaters into the netlist before physical routing begins. This allows the routing tool to automatically determine optimal repeater locations and topologies without requiring manual intervention during the routing process, thereby maintaining high routing quality while significantly reducing routing time.
Solution Approach 2:
The routing tool is enhanced to automatically perform repeater insertion and topology control without manual designer intervention. The tool serves itself by automatically analyzing net requirements, determining repeater placements, and generating appropriate routing topologies, eliminating the need for time-consuming manual custom routing while maintaining high performance standards.
2Reliability
If manual repeater insertion and custom routing are performed, then timing performance and signal integrity are improved, but device complexity and process difficulty increase
Solution Approach 1:
The routing tool automatically performs repeater insertion and topology generation without manual intervention. The system analyzes each net's requirements and automatically determines the appropriate repeater placement and routing topology, eliminating complex manual processes while maintaining timing performance and signal integrity.
Solution Approach 2:
The patent changes the parameter of repeater insertion from a manual post-routing operation to an automated pre-routing operation. By modifying when and how repeaters are inserted (changing the process parameter), the system maintains timing performance while dramatically simplifying the overall process complexity.
3Adaptability or versatility
If floor plan modifications are made at a later stage, then design adaptability is improved, but all custom routes must be re-done increasing loss of time
Solution Approach 1:
By inserting repeaters and establishing routing topologies in advance through automated tools, the system creates a flexible foundation that can accommodate floor plan modifications. When changes occur, the automated tool can quickly re-evaluate and adjust routes without requiring manual re-work of custom routing, thus maintaining design adaptability while minimizing re-routing time.
4Reliability
If repeaters are inserted after initial routing, then transition time requirements are met, but additional rip and re-route operations are needed increasing loss of time
Solution Approach 1:
The patent reverses the conventional sequence by inserting repeaters before physical routing instead of after. This preliminary action allows the routing tool to incorporate repeater locations into the routing planning from the beginning, eliminating the need for subsequent rip and re-route operations while still meeting transition time requirements.
Solution Approach 2:
The patent inverts the conventional routing process sequence. Instead of routing first and then inserting repeaters, the system inserts repeaters first and then performs routing. This inversion eliminates the need for additional re-routing operations while achieving the same transition time goals.
Data Source
AI summary
A method for routing a chip, involving forming a plurality of nets configured to connect components of the chip, wherein each of the plurality of nets is included in a netlist, assigning at least one repeater to each of the plurality of nets in the netlist, wherein the repeaters are assigned prior to performing physical routing of the plurality of nets, inserting the at least one repeater in a corresponding net, wherein the insertion of the at least one repeater divides the corresponding net into at least two subnets, and performing the physical routing of the plurality of nets by connecting each of the subnets.