Parallel Loop Processing with Precedence Tagged Memory Access
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Solution Overview
Problem
Current digital computer systems face inefficiencies in processing and presenting large amounts of data due to challenges in handling memory access hazards and latency, which can lead to stalls in processing operations, especially when dealing with multiple, independent loops.
Innovation Solution
A two-dimensional array of compute elements is accessed, where each compute element is coupled to its neighbors, and control is provided on a cycle-by-cycle basis using wide control words generated by a compiler. Memory access operations are tagged with precedence information to order loads and stores, avoiding hazards by delaying data promotion and using hardware to derive precedence values for proper ordering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple independent loops are executed in parallel, then productivity is improved, but memory access hazards and latency cause processing stalls
Solution Approach 1:
The patent applies preliminary action by tagging memory access operations with precedence information before execution. The compiler generates control words that include precedence tags for load and store operations, allowing the hardware to pre-determine the correct execution order of memory operations across multiple parallel loops without actual stalls, thus eliminating latency while maintaining productivity
2Reliability
If memory access operations are ordered to avoid hazards, then reliability is improved, but device complexity increases due to precedence tracking
Solution Approach 1:
The patent uses an intermediary approach by introducing precedence information tags as a mediator between the compiler and hardware execution. These tags are embedded in control words and serve as intermediate metadata that guide the memory access ordering without requiring complex runtime analysis or additional hardware structures, thus improving reliability while minimizing added complexity
3Productivity
If compute elements operate autonomously, then productivity is improved, but difficulty in detecting and measuring execution state increases
Solution Approach 1:
The patent implements feedback by having each compute element generate completion notifications that are sent back to the control unit when loop execution is finished. This feedback mechanism allows the system to track the execution state of autonomous compute elements without reducing their independence, enabling proper coordination and maintaining productivity while solving the detection difficulty
Data Source
AI summary
Techniques for parallel processing of multiple loops with loads and stores are disclosed. A two-dimensional array of compute elements is accessed. Each compute element within the array is known to a compiler and is coupled to its neighboring compute elements within the array. Control for the compute elements is provided on a cycle-by-cycle basis. Control is enabled by a stream of wide control words generated by the compiler. Memory access operations are tagged with precedence information. The tagging is contained in the control words and is implemented for loop operations. The tagging is provided by the compiler at compile time. Control word data is loaded for multiple, independent loops into the compute elements. The multiple, independent loops are executed. Memory is accessed based on the precedence information. The memory access includes loads and/or stores for data relating to the independent loops.