Architecture With Multiple Processing Units TRIZ Cases
- SIMD Vector Shift Instruction for Single-Step Register Operations
A single SIMD vector shift instruction replaces multi-step register operations, cutting instruction overhead and improving execution efficiency.
- Array Processor with Macro-Instructions for Zero-Latency Data Movement
Programmable macro-instructions configure N-dimensional arrays to reduce data movement latency while maintaining modular architecture complexity.
- Configurable Spatial Accelerator Sign Modification for Energy Efficiency
A configurable spatial accelerator modifies sign bits to perform fused operations without complex control overheads.
- Vector Processor DMA Configuration for Feature Tracking
Hardware sequencers in the DMA system reduce programming complexity while decoupled accelerators increase throughput for computer vision tasks.
- Descriptor Synchronization for Neural Network Data Processing
A descriptor synchronization instruction transmits tensor metadata to processors.
- SIMD Multi-Stage Cube Network Data Movement
Multi-stage cube networks reduce hardware costs and improve scalability by segmenting N-input multiplexors into log2(N) stages of 2x2 switches.
- Compute-In-Memory Convolution via Vector-Matrix Multiplication
Compute-in-memory modules execute vector-matrix multiplications to bypass nested loop inefficiencies in learning networks.
- Parallel Primitive Distribution to Multiple Rasterizers
A primitive distribution scheme delivers graphics primitives concurrently to multiple rasterizers via a crossbar fabric.
- Adjoining Data Element Pairwise Swap Processor Instruction
An adjoining data element pairwise swap instruction reduces instruction length and power consumption by eliminating flexible shuffle control bits.
- Matrix Processor Circuit Data Reshape and Transport
Matrix processor circuits reshape data to minimize movement latency, reducing idle time in AI workloads.
- Asymmetrical Processor Memory Architecture Reducing Data Movement
Merging scalar and vector memory spaces reduces data transfer time and power consumption by enabling parallel processing within a single memory region.
- Composite Node Interconnection for Reduced Chip Count
Segmenting a computing system into composite nodes with multi-function node controllers reduces interconnection structure complexity and access delays.
- Configurable Switch Network for Sorted Array Intersection
Hardware switches perform sorted array intersections to reduce synchronization latency and improve parallel processing efficiency.