Vector Processor DMA Configuration for Feature Tracking
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Solution Overview
Problem
Conventional vector processing units (VPUs) face inefficiencies in detecting min/max values, operand sharing, memory access, data manipulation, and fault detection, leading to increased latency and processing complexity in applications like computer vision and deep learning.
Innovation Solution
The proposed solution includes a min/max hardware collector, automatic predication, enhanced SIMD architecture with lane communication, transposed load/store operations, load with permute instructions, and a decoupled DMA system to reduce latency and improve throughput by enabling immediate availability of min/max values, efficient operand sharing, optimized memory access, and reduced programming complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional VPU executes SIMD operations with independent data lanes, then parallel processing capability is improved, but operand sharing between lanes becomes difficult and requires copying operations
Solution Approach 1:
The patent merges operand sharing capability into the SIMD architecture by enabling adjacent data lanes to share operands directly. This eliminates the need for separate copying operations and reduces the complexity of implementing operand sharing while maintaining parallel processing benefits.
Solution Approach 2:
The SIMD data lanes are designed to have both independent processing capability and shared operand access capability. This multi-functionality allows the same architectural components to support both parallel independent operations and efficient operand sharing, reducing overall system complexity.
2Ease of operation
If VPU uses standard memory read operations with consistent units, then memory access simplicity is improved, but memory bandwidth utilization becomes inefficient when reading partial ranges
Solution Approach 1:
The patent implements partial read operations that allow the VPU to read only the specific memory range needed (e.g., elements 4 to 67) rather than reading complete standard units. This partial action approach maintains operational simplicity while significantly improving memory bandwidth utilization efficiency by avoiding unnecessary reads.
3Adaptability or versatility
If VPU performs additional data manipulation instructions after memory reads, then data reorganization capability is improved, but processing latency increases due to additional cycles
Solution Approach 1:
The patent performs data reorganization and manipulation operations during the memory read process itself rather than as subsequent steps. By completing the data reorganization action preliminarily during the read operation, the system eliminates additional latency cycles while maintaining full data reorganization capability.
4Speed
If VPU implements hardware min/max collection, then anomaly detection speed is improved, but device complexity increases due to additional hardware components
Solution Approach 1:
The patent merges the min/max collection functionality into the existing VPU data path by utilizing existing registers and comparison logic. This integration approach enables hardware-based anomaly detection at high speed while minimizing additional hardware complexity by reusing existing architectural components.
5Measurement precision
If DMA system requires processing controller intervention for unknown data, then data movement accuracy is improved, but processing latency and programming complexity increase
Solution Approach 1:
The patent implements self-service data movement in the DMA system where the DMA controller automatically determines and updates memory addressing information without requiring processing controller intervention. This self-service capability maintains data movement accuracy while eliminating the latency and programming complexity associated with external controller involvement.
Data Source
AI summary
In various examples, a VPU and associated components may be optimized to improve VPU performance and throughput. For example, the VPU may include a min/max collector, automatic store predication functionality, a SIMD data path organization that allows for inter-lane sharing, a transposed load/store with stride parameter functionality, a load with permute and zero insertion functionality, hardware, logic, and memory layout functionality to allow for two point and two by two point lookups, and per memory bank load caching capabilities. In addition, decoupled accelerators may be used to offload VPU processing tasks to increase throughput and performance, and a hardware sequencer may be included in a DMA system to reduce programming complexity of the VPU and the DMA system. The DMA and VPU may execute a VPU configuration mode that allows the VPU and DMA to operate without a processing controller for performing dynamic region based data movement operations.